From: Fabiano Rosas <faro...@linux.ibm.com>
The 405 ISI does not set SRR1 with any exception syndrome bits, only a
clean copy of the MSR.
Signed-off-by: Fabiano Rosas <faro...@linux.ibm.com>
Reviewed-by: Cédric Le Goater <c...@kaod.org>
[ clg : Fixed removal which was done in the wrong routine ]
Message-Id: <20220118184448.852996-13-faro...@linux.ibm.com>
Signed-off-by: Cédric Le Goater <c...@kaod.org>
---
target/ppc/excp_helper.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
index deba12f4f367..7d89bd0651d8 100644
--- a/target/ppc/excp_helper.c
+++ b/target/ppc/excp_helper.c
@@ -469,7 +469,6 @@ static void powerpc_excp_40x(PowerPCCPU *cpu, int excp)
break;
case POWERPC_EXCP_ISI: /* Instruction storage exception */
trace_ppc_excp_isi(msr, env->nip);
- msr |= env->error_code;
break;
case POWERPC_EXCP_EXTERNAL: /* External input */
break;
--
2.34.1
