On Thu, 10 Feb 2022 at 04:05, Richard Henderson <richard.hender...@linaro.org> wrote: > > This feature widens physical addresses (and intermediate physical > addresses for 2-stage translation) from 48 to 52 bits, when using > 64k pages. The only thing left at this point is to handle the > extra bits in the TTBR and in the table descriptors. > > Note that PAR_EL1 and HPFAR_EL2 are nominally extended, but we don't > mask out the high bits when writing to those registers, so no changes > are required there. > > Reviewed-by: Peter Maydell <peter.mayd...@linaro.org> > Signed-off-by: Richard Henderson <richard.hender...@linaro.org> > --- > target/arm/cpu-param.h | 2 +- > target/arm/cpu64.c | 2 +- > target/arm/helper.c | 19 ++++++++++++++++--- > 3 files changed, 18 insertions(+), 5 deletions(-)
Need to update docs/system/arm/emulation.rst -- PMM
