On Tue, Mar 1, 2022 at 10:06 PM Weiwei Li <liwei...@iscas.ac.cn> wrote: > > - add xperm4 and xperm8 instructions > > Signed-off-by: Weiwei Li <liwei...@iscas.ac.cn> > Signed-off-by: Junqiang Wang <wangjunqi...@iscas.ac.cn> > Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Acked-by: Alistair Francis <alistair.fran...@wdc.com> Alistair > --- > target/riscv/bitmanip_helper.c | 27 +++++++++++++++++++++++++ > target/riscv/helper.h | 2 ++ > target/riscv/insn32.decode | 4 ++++ > target/riscv/insn_trans/trans_rvb.c.inc | 18 +++++++++++++++++ > 4 files changed, 51 insertions(+) > > diff --git a/target/riscv/bitmanip_helper.c b/target/riscv/bitmanip_helper.c > index e003e8b25b..b99c4a39a1 100644 > --- a/target/riscv/bitmanip_helper.c > +++ b/target/riscv/bitmanip_helper.c > @@ -102,3 +102,30 @@ target_ulong HELPER(zip)(target_ulong rs1) > x = do_shuf_stage(x, shuf_masks[0], shuf_masks[0] >> 1, 1); > return x; > } > + > +static inline target_ulong do_xperm(target_ulong rs1, target_ulong rs2, > + uint32_t sz_log2) > +{ > + target_ulong r = 0; > + target_ulong sz = 1LL << sz_log2; > + target_ulong mask = (1LL << sz) - 1; > + target_ulong pos; > + > + for (int i = 0; i < TARGET_LONG_BITS; i += sz) { > + pos = ((rs2 >> i) & mask) << sz_log2; > + if (pos < sizeof(target_ulong) * 8) { > + r |= ((rs1 >> pos) & mask) << i; > + } > + } > + return r; > +} > + > +target_ulong HELPER(xperm4)(target_ulong rs1, target_ulong rs2) > +{ > + return do_xperm(rs1, rs2, 2); > +} > + > +target_ulong HELPER(xperm8)(target_ulong rs1, target_ulong rs2) > +{ > + return do_xperm(rs1, rs2, 3); > +} > diff --git a/target/riscv/helper.h b/target/riscv/helper.h > index 7331d32dbf..a1d28b257f 100644 > --- a/target/riscv/helper.h > +++ b/target/riscv/helper.h > @@ -69,6 +69,8 @@ DEF_HELPER_FLAGS_2(clmulr, TCG_CALL_NO_RWG_SE, tl, tl, tl) > DEF_HELPER_FLAGS_1(brev8, TCG_CALL_NO_RWG_SE, tl, tl) > DEF_HELPER_FLAGS_1(unzip, TCG_CALL_NO_RWG_SE, tl, tl) > DEF_HELPER_FLAGS_1(zip, TCG_CALL_NO_RWG_SE, tl, tl) > +DEF_HELPER_FLAGS_2(xperm4, TCG_CALL_NO_RWG_SE, tl, tl, tl) > +DEF_HELPER_FLAGS_2(xperm8, TCG_CALL_NO_RWG_SE, tl, tl, tl) > > /* Floating Point - Half Precision */ > DEF_HELPER_FLAGS_3(fadd_h, TCG_CALL_NO_RWG, i64, env, i64, i64) > diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode > index 3a49acab37..75ffac9c81 100644 > --- a/target/riscv/insn32.decode > +++ b/target/riscv/insn32.decode > @@ -776,6 +776,10 @@ clmulh 0000101 .......... 011 ..... 0110011 @r > # *** RV32 extra Zbc Standard Extension *** > clmulr 0000101 .......... 010 ..... 0110011 @r > > +# *** RV32 Zbkx Standard Extension *** > +xperm4 0010100 .......... 010 ..... 0110011 @r > +xperm8 0010100 .......... 100 ..... 0110011 @r > + > # *** RV32 Zbs Standard Extension *** > bclr 0100100 .......... 001 ..... 0110011 @r > bclri 01001. ........... 001 ..... 0010011 @sh > diff --git a/target/riscv/insn_trans/trans_rvb.c.inc > b/target/riscv/insn_trans/trans_rvb.c.inc > index 1980bfe971..54927ba763 100644 > --- a/target/riscv/insn_trans/trans_rvb.c.inc > +++ b/target/riscv/insn_trans/trans_rvb.c.inc > @@ -48,6 +48,12 @@ > } \ > } while (0) > > +#define REQUIRE_ZBKX(ctx) do { \ > + if (!ctx->cfg_ptr->ext_zbkx) { \ > + return false; \ > + } \ > +} while (0) > + > static void gen_clz(TCGv ret, TCGv arg1) > { > tcg_gen_clzi_tl(ret, arg1, TARGET_LONG_BITS); > @@ -574,3 +580,15 @@ static bool trans_zip(DisasContext *ctx, arg_zip *a) > REQUIRE_ZBKB(ctx); > return gen_unary(ctx, a, EXT_NONE, gen_helper_zip); > } > + > +static bool trans_xperm4(DisasContext *ctx, arg_xperm4 *a) > +{ > + REQUIRE_ZBKX(ctx); > + return gen_arith(ctx, a, EXT_NONE, gen_helper_xperm4, NULL); > +} > + > +static bool trans_xperm8(DisasContext *ctx, arg_xperm8 *a) > +{ > + REQUIRE_ZBKX(ctx); > + return gen_arith(ctx, a, EXT_NONE, gen_helper_xperm8, NULL); > +} > -- > 2.17.1 > >