Bin Meng <bmeng...@gmail.com> writes: > From: Bin Meng <bin.m...@windriver.com> > > Per E500 core reference manual [1], chapter 8.4.4 "Branch Taken Debug > Event" and chapter 8.4.5 "Instruction Complete Debug Event": > > "A branch taken debug event occurs if both MSR[DE] and DBCR0[BRT] > are set ... Branch taken debug events are not recognized if MSR[DE] > is cleared when the branch instruction executes." > > "An instruction complete debug event occurs when any instruction > completes execution so long as MSR[DE] and DBCR0[ICMP] are both > set ... Instruction complete debug events are not recognized if > MSR[DE] is cleared at the time of the instruction execution." > > Current codes do not check MSR.DE bit before setting HFLAGS_SE and > HFLAGS_BE flag, which would cause the immediate debug interrupt to > be generated, e.g.: when DBCR0.ICMP bit is set by guest software > and MSR.DE is not set. > > [1] https://www.nxp.com/docs/en/reference-manual/E500CORERM.pdf > > Signed-off-by: Bin Meng <bin.m...@windriver.com>
Reviewed-by: Fabiano Rosas <faro...@linux.ibm.com>
