[PATCH 2/3] target/ppc: Move tlbiel to decode tree

[Leandro Lupori]

Also decode RIC, PRS and R operands.

Signed-off-by: Leandro Lupori <leandro.lup...@eldorado.org.br>
---
 target/ppc/insn32.decode                     |  1 +
 target/ppc/translate.c                       | 22 --------------------
 target/ppc/translate/storage-ctrl-impl.c.inc | 16 +++++++++-----
 3 files changed, 12 insertions(+), 27 deletions(-)

diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
index fdfd24e8bd..79c38453fc 100644
--- a/target/ppc/insn32.decode
+++ b/target/ppc/insn32.decode
@@ -717,3 +717,4 @@ RFEBB           010011-------------- .   0010010010 -   
@XL_s
 @X_tlbie        ...... rs:5 - ric:2 prs:1 r:1 rb:5 .......... .     &X_tlbie
 
 TLBIE           011111 ..... - .. . . ..... 0100110010 -            @X_tlbie
+TLBIEL          011111 ..... - .. . . ..... 0100010010 -            @X_tlbie
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index 662bd20de5..2eb7dea800 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -5393,26 +5393,6 @@ static void gen_tlbia(DisasContext *ctx)
 #endif  /* defined(CONFIG_USER_ONLY) */
 }
 
-/* tlbiel */
-static void gen_tlbiel(DisasContext *ctx)
-{
-#if defined(CONFIG_USER_ONLY)
-    GEN_PRIV;
-#else
-    bool psr = (ctx->opcode >> 17) & 0x1;
-
-    if (ctx->pr || (!ctx->hv && !psr && ctx->hr)) {
-        /*
-         * tlbiel is privileged except when PSR=0 and HR=1, making it
-         * hypervisor privileged.
-         */
-        GEN_PRIV;
-    }
-
-    gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
-#endif /* defined(CONFIG_USER_ONLY) */
-}
-
 /* tlbsync */
 static void gen_tlbsync(DisasContext *ctx)
 {
@@ -6870,8 +6850,6 @@ GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, 
PPC_MEM_TLBIA),
  * XXX Those instructions will need to be handled differently for
  * different ISA versions
  */
-GEN_HANDLER(tlbiel, 0x1F, 0x12, 0x08, 0x001F0001, PPC_MEM_TLBIE),
-GEN_HANDLER_E(tlbiel, 0x1F, 0x12, 0x08, 0x00100001, PPC_NONE, PPC2_ISA300),
 GEN_HANDLER(tlbsync, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM_TLBSYNC),
 #if defined(TARGET_PPC64)
 GEN_HANDLER(slbia, 0x1F, 0x12, 0x0F, 0x031FFC01, PPC_SLBI),
diff --git a/target/ppc/translate/storage-ctrl-impl.c.inc 
b/target/ppc/translate/storage-ctrl-impl.c.inc
index 33733c082c..7793297dd4 100644
--- a/target/ppc/translate/storage-ctrl-impl.c.inc
+++ b/target/ppc/translate/storage-ctrl-impl.c.inc
@@ -46,21 +46,21 @@ static bool do_tlbie(DisasContext *ctx, arg_X_tlbie *a, 
bool local)
     }
 
     if (ctx->pr) {
-        /* tlbie is privileged... */
+        /* tlbie[l] is privileged... */
         gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC);
         return true;
     } else if (!ctx->hv) {
-        if (!ctx->gtse || (!a->prs && ctx->hr)) {
+        if ((!a->prs && ctx->hr) || (!local && !ctx->gtse)) {
             /*
-             * ... except when GTSE=0 or when PRS=0 and HR=1, making it
-             * hypervisor privileged.
+             * ... except when PRS=0 and HR=1, or when GTSE=0 for tlbie,
+             * making it hypervisor privileged.
              */
             gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC);
             return true;
         }
     }
 
-    if (NARROW_MODE(ctx)) {
+    if (!local && NARROW_MODE(ctx)) {
         TCGv t0 = tcg_temp_new();
         tcg_gen_ext32u_tl(t0, cpu_gpr[rb]);
         gen_helper_tlbie(cpu_env, t0);
@@ -68,6 +68,11 @@ static bool do_tlbie(DisasContext *ctx, arg_X_tlbie *a, bool 
local)
     } else {
         gen_helper_tlbie(cpu_env, cpu_gpr[rb]);
     }
+
+    if (local) {
+        return true;
+    }
+
     t1 = tcg_temp_new_i32();
     tcg_gen_ld_i32(t1, cpu_env, offsetof(CPUPPCState, tlb_need_flush));
     tcg_gen_ori_i32(t1, t1, TLB_NEED_GLOBAL_FLUSH);
@@ -79,3 +84,4 @@ static bool do_tlbie(DisasContext *ctx, arg_X_tlbie *a, bool 
local)
 }
 
 TRANS_FLAGS(MEM_TLBIE, TLBIE, do_tlbie, false)
+TRANS_FLAGS(MEM_TLBIE, TLBIEL, do_tlbie, true)
-- 
2.25.1