On 6/7/22 03:03, Peter Maydell wrote:
On Thu, 2 Jun 2022 at 23:41, Richard Henderson
<richard.hender...@linaro.org> wrote:
This includes the build rules for the decoder, and the
new file for translation, but excludes any instructions.
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
@@ -14814,7 +14814,12 @@ static void aarch64_tr_translate_insn(DisasContextBase
*dcbase, CPUState *cpu)
}
switch (extract32(insn, 25, 4)) {
- case 0x0: case 0x1: case 0x3: /* UNALLOCATED */
+ case 0x0:
+ if (!disas_sme(s, insn)) {
+ unallocated_encoding(s);
+ }
+ break;
+ case 0x1: case 0x3: /* UNALLOCATED */
unallocated_encoding(s);
break;
case 0x2:
This is grabbing slightly more of the encoding space than it should
according to the Arm ARM Table C4-1 "Main encoding table": SME
encodings require bit 31 == 1 (unlike SVE where bit 31 is not decoded
at this level).
Yeah, well, full and proper decode is done in the generated decoder.
I don't feel the need to distinguish that bit here.
r~
Otherwise
Reviewed-by: Peter Maydell <peter.mayd...@linaro.org>
thanks
-- PMM
