From: Niccolò Izzo <ni...@rev.ng>
These helpers will be employed by the idef-parser generated code, to
correctly implement instruction semantics. "Helper" functions, in the
context of this patch, refers to functions which provide a manual TCG
implementation of certain features.
Signed-off-by: Alessandro Di Federico <a...@rev.ng>
Signed-off-by: Niccolò Izzo <ni...@rev.ng>
Signed-off-by: Anton Johansson <a...@rev.ng>
Reviewed-by: Taylor Simpson <tsimp...@quicinc.com>
---
target/hexagon/genptr.c | 178 ++++++++++++++++++++++++++++++++++++++--
target/hexagon/genptr.h | 17 +++-
target/hexagon/macros.h | 9 ++
3 files changed, 196 insertions(+), 8 deletions(-)
diff --git a/target/hexagon/genptr.c b/target/hexagon/genptr.c
index 000e9813c5..ab04e5e7ff 100644
--- a/target/hexagon/genptr.c
+++ b/target/hexagon/genptr.c
@@ -31,6 +31,12 @@
#include "gen_tcg_hvx.h"
#include "genptr.h"
+TCGv gen_read_reg(TCGv result, int num)
+{
+ tcg_gen_mov_tl(result, hex_gpr[num]);
+ return result;
+}
+
TCGv gen_read_preg(TCGv pred, uint8_t num)
{
tcg_gen_mov_tl(pred, hex_pred[num]);
@@ -403,18 +409,19 @@ static inline void gen_store_conditional8(DisasContext
*ctx,
tcg_gen_movi_tl(hex_llsc_addr, ~0);
}
-void gen_store32(TCGv vaddr, TCGv src, int width, uint32_t slot)
+void gen_store32(DisasContext *ctx, TCGv vaddr, TCGv src, tcg_target_long
width,
+ uint32_t slot)
{
tcg_gen_mov_tl(hex_store_addr[slot], vaddr);
tcg_gen_movi_tl(hex_store_width[slot], width);
tcg_gen_mov_tl(hex_store_val32[slot], src);
+ ctx->store_width[slot] = width;
}
void gen_store1(TCGv_env cpu_env, TCGv vaddr, TCGv src, DisasContext *ctx,
uint32_t slot)
{
- gen_store32(vaddr, src, 1, slot);
- ctx->store_width[slot] = 1;
+ gen_store32(ctx, vaddr, src, 1, slot);
}
void gen_store1i(TCGv_env cpu_env, TCGv vaddr, int32_t src, DisasContext *ctx,
@@ -427,8 +434,7 @@ void gen_store1i(TCGv_env cpu_env, TCGv vaddr, int32_t src,
DisasContext *ctx,
void gen_store2(TCGv_env cpu_env, TCGv vaddr, TCGv src, DisasContext *ctx,
uint32_t slot)
{
- gen_store32(vaddr, src, 2, slot);
- ctx->store_width[slot] = 2;
+ gen_store32(ctx, vaddr, src, 2, slot);
}
void gen_store2i(TCGv_env cpu_env, TCGv vaddr, int32_t src, DisasContext *ctx,
@@ -441,8 +447,7 @@ void gen_store2i(TCGv_env cpu_env, TCGv vaddr, int32_t src,
DisasContext *ctx,
void gen_store4(TCGv_env cpu_env, TCGv vaddr, TCGv src, DisasContext *ctx,
uint32_t slot)
{
- gen_store32(vaddr, src, 4, slot);
- ctx->store_width[slot] = 4;
+ gen_store32(ctx, vaddr, src, 4, slot);
}
void gen_store4i(TCGv_env cpu_env, TCGv vaddr, int32_t src, DisasContext *ctx,
@@ -654,5 +659,164 @@ void probe_noshuf_load(TCGv va, int s, int mi)
gen_helper_probe_noshuf_load(cpu_env, va, size, mem_idx);
}
+void gen_set_usr_field(int field, TCGv val)
+{
+ tcg_gen_deposit_tl(hex_new_value[HEX_REG_USR], hex_new_value[HEX_REG_USR],
+ val,
+ reg_field_info[field].offset,
+ reg_field_info[field].width);
+}
+
+void gen_set_usr_fieldi(int field, int x)
+{
+ TCGv val = tcg_constant_tl(x);
+ gen_set_usr_field(field, val);
+}
+
+/*
+ * Note: Since this function might branch, `val` is
+ * required to be a `tcg_temp_local`.
+ */
+void gen_set_usr_field_if(int field, TCGv val)
+{
+ /* Sets the USR field if `val` is non-zero */
+ if (reg_field_info[field].width == 1) {
+ TCGv tmp = tcg_temp_new();
+ tcg_gen_extract_tl(tmp, val, 0, reg_field_info[field].width);
+ tcg_gen_shli_tl(tmp, tmp, reg_field_info[field].offset);
+ tcg_gen_or_tl(hex_new_value[HEX_REG_USR],
+ hex_new_value[HEX_REG_USR],
+ tmp);
+ tcg_temp_free(tmp);
+ } else {
+ TCGLabel *skip_label = gen_new_label();
+ tcg_gen_brcondi_tl(TCG_COND_EQ, val, 0, skip_label);
+ gen_set_usr_field(field, val);
+ gen_set_label(skip_label);
+ }
+}
+
+void gen_write_new_pc(TCGv addr)
+{
+ /* If there are multiple branches in a packet, ignore the second one */
+ TCGv zero = tcg_constant_tl(0);
+ tcg_gen_movcond_tl(TCG_COND_NE, hex_next_PC, hex_branch_taken, zero,
+ hex_next_PC, addr);
+ tcg_gen_movi_tl(hex_branch_taken, 1);
+}
+
+void gen_sat_i32(TCGv dest, TCGv source, int width)
+{
+ TCGv max_val = tcg_constant_tl((1 << (width - 1)) - 1);
+ TCGv min_val = tcg_constant_tl(-(1 << (width - 1)));
+ tcg_gen_smin_tl(dest, source, max_val);
+ tcg_gen_smax_tl(dest, dest, min_val);
+}
+
+void gen_sat_i32_ovfl(TCGv ovfl, TCGv dest, TCGv source, int width)
+{
+ gen_sat_i32(dest, source, width);
+ tcg_gen_setcond_tl(TCG_COND_NE, ovfl, source, dest);
+}
+
+void gen_satu_i32(TCGv dest, TCGv source, int width)
+{
+ TCGv max_val = tcg_constant_tl((1 << width) - 1);
+ TCGv zero = tcg_constant_tl(0);
+ tcg_gen_movcond_tl(TCG_COND_GTU, dest, source, max_val, max_val, source);
+ tcg_gen_movcond_tl(TCG_COND_LT, dest, source, zero, zero, dest);
+}
+
+void gen_satu_i32_ovfl(TCGv ovfl, TCGv dest, TCGv source, int width)
+{
+ gen_satu_i32(dest, source, width);
+ tcg_gen_setcond_tl(TCG_COND_NE, ovfl, source, dest);
+}
+
+void gen_sat_i64(TCGv_i64 dest, TCGv_i64 source, int width)
+{
+ TCGv_i64 max_val = tcg_constant_i64((1LL << (width - 1)) - 1LL);
+ TCGv_i64 min_val = tcg_constant_i64(-(1LL << (width - 1)));
+ tcg_gen_smin_i64(dest, source, max_val);
+ tcg_gen_smax_i64(dest, dest, min_val);
+}
+
+void gen_sat_i64_ovfl(TCGv ovfl, TCGv_i64 dest, TCGv_i64 source, int width)
+{
+ TCGv_i64 ovfl_64;
+ gen_sat_i64(dest, source, width);
+ ovfl_64 = tcg_temp_new_i64();
+ tcg_gen_setcond_i64(TCG_COND_NE, ovfl_64, dest, source);
+ tcg_gen_trunc_i64_tl(ovfl, ovfl_64);
+ tcg_temp_free_i64(ovfl_64);
+}
+
+void gen_satu_i64(TCGv_i64 dest, TCGv_i64 source, int width)
+{
+ TCGv_i64 max_val = tcg_constant_i64((1LL << width) - 1LL);
+ TCGv_i64 zero = tcg_constant_i64(0);
+ tcg_gen_movcond_i64(TCG_COND_GTU, dest, source, max_val, max_val, source);
+ tcg_gen_movcond_i64(TCG_COND_LT, dest, source, zero, zero, dest);
+}
+
+void gen_satu_i64_ovfl(TCGv ovfl, TCGv_i64 dest, TCGv_i64 source, int width)
+{
+ TCGv_i64 ovfl_64;
+ gen_satu_i64(dest, source, width);
+ ovfl_64 = tcg_temp_new_i64();
+ tcg_gen_setcond_i64(TCG_COND_NE, ovfl_64, dest, source);
+ tcg_gen_trunc_i64_tl(ovfl, ovfl_64);
+ tcg_temp_free_i64(ovfl_64);
+}
+
+/* Implements the fADDSAT64 macro in TCG */
+void gen_add_sat_i64(TCGv_i64 ret, TCGv_i64 a, TCGv_i64 b)
+{
+ TCGv_i64 sum = tcg_temp_local_new_i64();
+ TCGv_i64 xor = tcg_temp_new_i64();
+ TCGv_i64 cond1 = tcg_temp_new_i64();
+ TCGv_i64 cond2 = tcg_temp_local_new_i64();
+ TCGv_i64 cond3 = tcg_temp_new_i64();
+ TCGv_i64 mask = tcg_constant_i64(0x8000000000000000ULL);
+ TCGv_i64 max_pos = tcg_constant_i64(0x7FFFFFFFFFFFFFFFLL);
+ TCGv_i64 max_neg = tcg_constant_i64(0x8000000000000000LL);
+ TCGv_i64 zero = tcg_constant_i64(0);
+ TCGLabel *no_ovfl_label = gen_new_label();
+ TCGLabel *ovfl_label = gen_new_label();
+ TCGLabel *ret_label = gen_new_label();
+
+ tcg_gen_add_i64(sum, a, b);
+ tcg_gen_xor_i64(xor, a, b);
+
+ /* if (xor & mask) */
+ tcg_gen_and_i64(cond1, xor, mask);
+ tcg_temp_free_i64(xor);
+ tcg_gen_brcondi_i64(TCG_COND_NE, cond1, 0, no_ovfl_label);
+ tcg_temp_free_i64(cond1);
+
+ /* else if ((a ^ sum) & mask) */
+ tcg_gen_xor_i64(cond2, a, sum);
+ tcg_gen_and_i64(cond2, cond2, mask);
+ tcg_gen_brcondi_i64(TCG_COND_NE, cond2, 0, ovfl_label);
+ tcg_temp_free_i64(cond2);
+ /* fallthrough to no_ovfl_label branch */
+
+ /* if branch */
+ gen_set_label(no_ovfl_label);
+ tcg_gen_mov_i64(ret, sum);
+ tcg_gen_br(ret_label);
+
+ /* else if branch */
+ gen_set_label(ovfl_label);
+ tcg_gen_and_i64(cond3, sum, mask);
+ tcg_temp_free_i64(mask);
+ tcg_temp_free_i64(sum);
+ tcg_gen_movcond_i64(TCG_COND_NE, ret, cond3, zero, max_pos, max_neg);
+ tcg_temp_free_i64(cond3);
+ SET_USR_FIELD(USR_OVF, 1);
+
+ gen_set_label(ret_label);
+}
+
#include "tcg_funcs_generated.c.inc"
#include "tcg_func_table_generated.c.inc"
diff --git a/target/hexagon/genptr.h b/target/hexagon/genptr.h
index 016d5d7085..6c50c5383b 100644
--- a/target/hexagon/genptr.h
+++ b/target/hexagon/genptr.h
@@ -24,7 +24,8 @@
extern const SemanticInsn opcode_genptr[];
-void gen_store32(TCGv vaddr, TCGv src, int width, uint32_t slot);
+void gen_store32(DisasContext *ctx, TCGv vaddr, TCGv src, tcg_target_long
width,
+ uint32_t slot);
void gen_store1(TCGv_env cpu_env, TCGv vaddr, TCGv src, DisasContext *ctx,
uint32_t slot);
void gen_store2(TCGv_env cpu_env, TCGv vaddr, TCGv src, DisasContext *ctx,
@@ -41,9 +42,23 @@ void gen_store4i(TCGv_env cpu_env, TCGv vaddr, int32_t src,
DisasContext *ctx,
uint32_t slot);
void gen_store8i(TCGv_env cpu_env, TCGv vaddr, int64_t src, DisasContext *ctx,
uint32_t slot);
+TCGv gen_read_reg(TCGv result, int num);
TCGv gen_read_preg(TCGv pred, uint8_t num);
void gen_log_reg_write(int rnum, TCGv val);
void gen_log_pred_write(DisasContext *ctx, int pnum, TCGv val);
+void gen_write_new_pc(TCGv addr);
+void gen_set_usr_field(int field, TCGv val);
+void gen_set_usr_fieldi(int field, int x);
+void gen_set_usr_field_if(int field, TCGv val);
+void gen_sat_i32(TCGv dest, TCGv source, int width);
+void gen_sat_i32_ovfl(TCGv ovfl, TCGv dest, TCGv source, int width);
+void gen_satu_i32(TCGv dest, TCGv source, int width);
+void gen_satu_i32_ovfl(TCGv ovfl, TCGv dest, TCGv source, int width);
+void gen_sat_i64(TCGv_i64 dest, TCGv_i64 source, int width);
+void gen_sat_i64_ovfl(TCGv ovfl, TCGv_i64 dest, TCGv_i64 source, int width);
+void gen_satu_i64(TCGv_i64 dest, TCGv_i64 source, int width);
+void gen_satu_i64_ovfl(TCGv ovfl, TCGv_i64 dest, TCGv_i64 source, int width);
+void gen_add_sat_i64(TCGv_i64 ret, TCGv_i64 a, TCGv_i64 b);
TCGv gen_8bitsof(TCGv result, TCGv value);
void gen_set_byte_i64(int N, TCGv_i64 result, TCGv src);
TCGv gen_get_byte(TCGv result, int N, TCGv src, bool sign);
diff --git a/target/hexagon/macros.h b/target/hexagon/macros.h
index 4529af107a..4c2e3ce21e 100644
--- a/target/hexagon/macros.h
+++ b/target/hexagon/macros.h
@@ -197,7 +197,16 @@
#define MEM_STORE8(VA, DATA, SLOT) log_store64(env, VA, DATA, 8, SLOT)
#endif
+#ifdef QEMU_GENERATE
+static inline void gen_cancel(uint32_t slot)
+{
+ tcg_gen_ori_tl(hex_slot_cancelled, hex_slot_cancelled, 1 << slot);
+}
+
+#define CANCEL gen_cancel(slot);
+#else
#define CANCEL cancel_slot(env, slot)
+#endif
#define LOAD_CANCEL(EA) do { CANCEL; } while (0)
--
2.37.0
