On Fri, 2022-08-19 at 00:55 +0800, Vivian Wang wrote: > Hi, > Could this be related to issue 1155 [1]? On RISC-V, I'm getting > incorrect [m|s]tval/[m|s]epc combinations for page faults in system > emulation and incorrect si_addr and program counter on SIGSEGV in > user emulation. Since it seems to only affect instructions that cross > page boundaries, and RISC-V also has variable length instructions, it > seems that I've run into the same problem as what is fixed here. > Could this fix be extended be extended to targets/riscv? > dram > [1]: https://gitlab.com/qemu-project/qemu/-/issues/1155
Yes, this looks quite similar. I'm not too familiar with riscv, but I just googled [1]. If the following is correct: --- However, the instruction set reserves enough opcode space to make it possible to differentiate between 16-bit, 32-bit, 48-bit, and 64-bit instructions. Instructions that start with binary 11 (in the lowest bit position of the instruction) are 32-bit sized instructions (but one pattern is reserved: so they cannot start with 11111). The compact instructions use 00, 01, and 10 in that same position. 48-bit instructions use starting sequence 011111, and 64-bit instructions start with 0111111. --- then we can fix this the same way s390x is being fixed here. [1] https://stackoverflow.com/questions/56874101/how-does-risc-v-variable-length-of-instruction-work-in-detail
