On 8/22/22 06:23, Peter Maydell wrote:
FEAT_PMUv3p5 introduces new bits which disable the cycle
counter from counting:
* MDCR_EL2.HCCD disables the counter when in EL2
* MDCR_EL3.SCCD disables the counter when Secure
Add the code to support these bits.
(Note that there is a third documented counter-disable
bit, MDCR_EL3.MCCD, which disables the counter when in
EL3. This is not present until FEAT_PMUv3p7, so is
out of scope for now.)
Signed-off-by: Peter Maydell<peter.mayd...@linaro.org>
---
v1->v2: Get the MDCR_EL3 bit right; v1 implemented something
more like MDCR_EL3.MCCD.
---
target/arm/cpu.h | 20 ++++++++++++++++++++
target/arm/helper.c | 21 +++++++++++++++++----
2 files changed, 37 insertions(+), 4 deletions(-)
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
r~
