Hi; this is the latest target-arm queue; most of this is a refactoring patchset from RTH for the arm page-table-walk emulation.
thanks -- PMM The following changes since commit f1d33f55c47dfdaf8daacd618588ad3ae4c452d1: Merge tag 'pull-testing-gdbstub-plugins-gitdm-061022-3' of https://github.com/stsquad/qemu into staging (2022-10-06 07:11:56 -0400) are available in the Git repository at: https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20221010 for you to fetch changes up to 915f62844cf62e428c7c178149b5ff1cbe129b07: docs/system/arm/emulation.rst: Report FEAT_GTG support (2022-10-10 14:52:25 +0100) ---------------------------------------------------------------- target-arm queue: * Retry KVM_CREATE_VM call if it fails EINTR * allow setting SCR_EL3.EnTP2 when FEAT_SME is implemented * docs/nuvoton: Update URL for images * refactoring of page table walk code * hw/arm/boot: set CPTR_EL3.ESM and SCR_EL3.EnTP2 when booting Linux with EL3 * Don't allow guest to use unimplemented granule sizes * Report FEAT_GTG support ---------------------------------------------------------------- Jerome Forissier (2): target/arm: allow setting SCR_EL3.EnTP2 when FEAT_SME is implemented hw/arm/boot: set CPTR_EL3.ESM and SCR_EL3.EnTP2 when booting Linux with EL3 Joel Stanley (1): docs/nuvoton: Update URL for images Peter Maydell (4): target/arm/kvm: Retry KVM_CREATE_VM call if it fails EINTR target/arm: Don't allow guest to use unimplemented granule sizes target/arm: Use ARMGranuleSize in ARMVAParameters docs/system/arm/emulation.rst: Report FEAT_GTG support Richard Henderson (21): target/arm: Split s2walk_secure from ipa_secure in get_phys_addr target/arm: Make the final stage1+2 write to secure be unconditional target/arm: Add is_secure parameter to get_phys_addr_lpae target/arm: Fix S2 disabled check in S1_ptw_translate target/arm: Add is_secure parameter to regime_translation_disabled target/arm: Split out get_phys_addr_with_secure target/arm: Add is_secure parameter to v7m_read_half_insn target/arm: Add TBFLAG_M32.SECURE target/arm: Merge regime_is_secure into get_phys_addr target/arm: Add is_secure parameter to do_ats_write target/arm: Fold secure and non-secure a-profile mmu indexes target/arm: Reorg regime_translation_disabled target/arm: Drop secure check for HCR.TGE vs SCTLR_EL1.M target/arm: Introduce arm_hcr_el2_eff_secstate target/arm: Hoist read of *is_secure in S1_ptw_translate target/arm: Remove env argument from combined_attrs_fwb target/arm: Pass HCR to attribute subroutines. target/arm: Fix ATS12NSO* from S PL1 target/arm: Split out get_phys_addr_disabled target/arm: Fix cacheattr in get_phys_addr_disabled target/arm: Use tlb_set_page_full docs/system/arm/emulation.rst | 1 + docs/system/arm/nuvoton.rst | 4 +- target/arm/cpu-param.h | 2 +- target/arm/cpu.h | 181 ++++++++------ target/arm/internals.h | 150 ++++++----- hw/arm/boot.c | 4 + target/arm/helper.c | 332 ++++++++++++++---------- target/arm/kvm.c | 4 +- target/arm/m_helper.c | 29 ++- target/arm/ptw.c | 570 ++++++++++++++++++++++-------------------- target/arm/tlb_helper.c | 9 +- target/arm/translate-a64.c | 8 - target/arm/translate.c | 9 +- 13 files changed, 717 insertions(+), 586 deletions(-)
