Queued in gitlab.com/danielhb/qemu/tree/ppc-next.
Phil, your acks for these patches are using the f4...@amsat.org email. Let me know if you want to use your new work address instead. Thanks, Daniel On 10/19/22 13:02, BALATON Zoltan wrote:
This is the end of the QOMify series originially started by Cédric rebased on master now only including patches not yet merged. Patches that still need review are 1-3 (these only move code to ppc4xx_sdram.c) and 6-7 (unify DDR and DDR2 models to share code where possible). Regards, BALATON Zoltan v7: Rebase on master after merge of first part of the series v6: Split patch moving sdram controller models together into smaller steps v5: Add functions the enable sdram controller and call it from boards v4: address more review comments v3: Fix patches that got squashed during rebase v2: address some review comments and try to avoid compile problem with gcc 12.2 (untested) BALATON Zoltan (8): ppc440_uc.c: Move DDR2 SDRAM controller model to ppc4xx_sdram.c ppc4xx_devs.c: Move DDR SDRAM controller model to ppc4xx_sdram.c ppc4xx_sdram: Move ppc4xx_sdram_banks() to ppc4xx_sdram.c ppc4xx_sdram: Use hwaddr for memory bank size ppc4xx_sdram: Rename local state variable for brevity ppc4xx_sdram: Generalise bank setup ppc4xx_sdram: Convert DDR SDRAM controller to new bank handling ppc4xx_sdram: Add errp parameter to ppc4xx_sdram_banks() hw/ppc/meson.build | 3 +- hw/ppc/ppc440_uc.c | 332 ------------------ hw/ppc/ppc4xx_devs.c | 414 ---------------------- hw/ppc/ppc4xx_sdram.c | 757 ++++++++++++++++++++++++++++++++++++++++ hw/ppc/trace-events | 1 + include/hw/ppc/ppc4xx.h | 20 +- 6 files changed, 768 insertions(+), 759 deletions(-) create mode 100644 hw/ppc/ppc4xx_sdram.c
