This patch includes:
- VEXTH.{H.B/W.H/D.W/Q.D};
- VEXTH.{HU.BU/WU.HU/DU.WU/QU.DU}.
Signed-off-by: Song Gao <gaos...@loongson.cn>
---
target/loongarch/disas.c | 9 ++++
target/loongarch/helper.h | 9 ++++
target/loongarch/insn_trans/trans_lsx.c.inc | 9 ++++
target/loongarch/insns.decode | 9 ++++
target/loongarch/lsx_helper.c | 49 +++++++++++++++++++++
5 files changed, 85 insertions(+)
diff --git a/target/loongarch/disas.c b/target/loongarch/disas.c
index 1ae085e192..3187f87bbe 100644
--- a/target/loongarch/disas.c
+++ b/target/loongarch/disas.c
@@ -1041,3 +1041,12 @@ INSN_LSX(vsat_bu, vv_i)
INSN_LSX(vsat_hu, vv_i)
INSN_LSX(vsat_wu, vv_i)
INSN_LSX(vsat_du, vv_i)
+
+INSN_LSX(vexth_h_b, vv)
+INSN_LSX(vexth_w_h, vv)
+INSN_LSX(vexth_d_w, vv)
+INSN_LSX(vexth_q_d, vv)
+INSN_LSX(vexth_hu_bu, vv)
+INSN_LSX(vexth_wu_hu, vv)
+INSN_LSX(vexth_du_wu, vv)
+INSN_LSX(vexth_qu_du, vv)
diff --git a/target/loongarch/helper.h b/target/loongarch/helper.h
index fc8044db51..7a9d4f125d 100644
--- a/target/loongarch/helper.h
+++ b/target/loongarch/helper.h
@@ -396,3 +396,12 @@ DEF_HELPER_4(vsat_bu, void, env, i32, i32, i32)
DEF_HELPER_4(vsat_hu, void, env, i32, i32, i32)
DEF_HELPER_4(vsat_wu, void, env, i32, i32, i32)
DEF_HELPER_4(vsat_du, void, env, i32, i32, i32)
+
+DEF_HELPER_3(vexth_h_b, void, env, i32, i32)
+DEF_HELPER_3(vexth_w_h, void, env, i32, i32)
+DEF_HELPER_3(vexth_d_w, void, env, i32, i32)
+DEF_HELPER_3(vexth_q_d, void, env, i32, i32)
+DEF_HELPER_3(vexth_hu_bu, void, env, i32, i32)
+DEF_HELPER_3(vexth_wu_hu, void, env, i32, i32)
+DEF_HELPER_3(vexth_du_wu, void, env, i32, i32)
+DEF_HELPER_3(vexth_qu_du, void, env, i32, i32)
diff --git a/target/loongarch/insn_trans/trans_lsx.c.inc
b/target/loongarch/insn_trans/trans_lsx.c.inc
index 09924343b2..48ea07b645 100644
--- a/target/loongarch/insn_trans/trans_lsx.c.inc
+++ b/target/loongarch/insn_trans/trans_lsx.c.inc
@@ -312,3 +312,12 @@ TRANS(vsat_bu, gen_vv_i, gen_helper_vsat_bu)
TRANS(vsat_hu, gen_vv_i, gen_helper_vsat_hu)
TRANS(vsat_wu, gen_vv_i, gen_helper_vsat_wu)
TRANS(vsat_du, gen_vv_i, gen_helper_vsat_du)
+
+TRANS(vexth_h_b, gen_vv, gen_helper_vexth_h_b)
+TRANS(vexth_w_h, gen_vv, gen_helper_vexth_w_h)
+TRANS(vexth_d_w, gen_vv, gen_helper_vexth_d_w)
+TRANS(vexth_q_d, gen_vv, gen_helper_vexth_q_d)
+TRANS(vexth_hu_bu, gen_vv, gen_helper_vexth_hu_bu)
+TRANS(vexth_wu_hu, gen_vv, gen_helper_vexth_wu_hu)
+TRANS(vexth_du_wu, gen_vv, gen_helper_vexth_du_wu)
+TRANS(vexth_qu_du, gen_vv, gen_helper_vexth_qu_du)
diff --git a/target/loongarch/insns.decode b/target/loongarch/insns.decode
index cae67533fd..8ae9ca608e 100644
--- a/target/loongarch/insns.decode
+++ b/target/loongarch/insns.decode
@@ -768,3 +768,12 @@ vsat_bu 0111 00110010 10000 01 ... ..... .....
@vv_ui3
vsat_hu 0111 00110010 10000 1 .... ..... ..... @vv_ui4
vsat_wu 0111 00110010 10001 ..... ..... ..... @vv_ui5
vsat_du 0111 00110010 1001 ...... ..... ..... @vv_ui6
+
+vexth_h_b 0111 00101001 11101 11000 ..... ..... @vv
+vexth_w_h 0111 00101001 11101 11001 ..... ..... @vv
+vexth_d_w 0111 00101001 11101 11010 ..... ..... @vv
+vexth_q_d 0111 00101001 11101 11011 ..... ..... @vv
+vexth_hu_bu 0111 00101001 11101 11100 ..... ..... @vv
+vexth_wu_hu 0111 00101001 11101 11101 ..... ..... @vv
+vexth_du_wu 0111 00101001 11101 11110 ..... ..... @vv
+vexth_qu_du 0111 00101001 11101 11111 ..... ..... @vv
diff --git a/target/loongarch/lsx_helper.c b/target/loongarch/lsx_helper.c
index 62ab14051e..a094d7d382 100644
--- a/target/loongarch/lsx_helper.c
+++ b/target/loongarch/lsx_helper.c
@@ -1780,3 +1780,52 @@ DO_HELPER_VV_I(vsat_bu, 8, helper_vv_i, do_vsat_u)
DO_HELPER_VV_I(vsat_hu, 16, helper_vv_i, do_vsat_u)
DO_HELPER_VV_I(vsat_wu, 32, helper_vv_i, do_vsat_u)
DO_HELPER_VV_I(vsat_du, 64, helper_vv_i, do_vsat_u)
+
+static void do_vexth_s(vec_t *Vd, vec_t *Vj, int bit, int n)
+{
+ switch (bit) {
+ case 16:
+ Vd->H[n] = Vj->B[n + LSX_LEN/bit];
+ break;
+ case 32:
+ Vd->W[n] = Vj->H[n + LSX_LEN/bit];
+ break;
+ case 64:
+ Vd->D[n] = Vj->W[n + LSX_LEN/bit];
+ break;
+ case 128:
+ Vd->Q[n] = Vj->D[n + LSX_LEN/bit];
+ break;
+ default:
+ g_assert_not_reached();
+ }
+}
+
+static void do_vexth_u(vec_t *Vd, vec_t *Vj, int bit, int n)
+{
+ switch (bit) {
+ case 16:
+ Vd->H[n] = (uint8_t)Vj->B[n + LSX_LEN/bit];
+ break;
+ case 32:
+ Vd->W[n] = (uint16_t)Vj->H[n + LSX_LEN/bit];
+ break;
+ case 64:
+ Vd->D[n] = (uint32_t)Vj->W[n + LSX_LEN/bit];
+ break;
+ case 128:
+ Vd->Q[n] = (uint64_t)Vj->D[n + LSX_LEN/bit];
+ break;
+ default:
+ g_assert_not_reached();
+ }
+}
+
+DO_HELPER_VV(vexth_h_b, 16, helper_vv, do_vexth_s)
+DO_HELPER_VV(vexth_w_h, 32, helper_vv, do_vexth_s)
+DO_HELPER_VV(vexth_d_w, 64, helper_vv, do_vexth_s)
+DO_HELPER_VV(vexth_q_d, 128, helper_vv, do_vexth_s)
+DO_HELPER_VV(vexth_hu_bu, 16, helper_vv, do_vexth_u)
+DO_HELPER_VV(vexth_wu_hu, 32, helper_vv, do_vexth_u)
+DO_HELPER_VV(vexth_du_wu, 64, helper_vv, do_vexth_u)
+DO_HELPER_VV(vexth_qu_du, 128, helper_vv, do_vexth_u)
--
2.31.1
