These settings are generic and identical between the two
host accelerators.
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
---
target/arm/cpu64.c | 23 ++++++++++++++++++++++-
target/arm/hvf/hvf.c | 13 +------------
target/arm/kvm.c | 29 ++---------------------------
3 files changed, 25 insertions(+), 40 deletions(-)
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
index 668e979a24..75a88f9deb 100644
--- a/target/arm/cpu64.c
+++ b/target/arm/cpu64.c
@@ -1090,6 +1090,21 @@ static void aarch64_neoverse_n1_class_init(ARMCPUClass
*cpu)
cpu->isar.reset_pmcr_el0 = 0x410c3000;
}
+static void aarch64_host_class_init(ARMCPUClass *acc)
+{
+ /*
+ * While we don't know all the host details, we can assume at
+ * least v8 with VFPv4+Neon; this in turn implies most of the
+ * other feature bits.
+ */
+ acc->dtb_compatible = "arm,arm-v8";
+ set_class_feature(acc, ARM_FEATURE_V8);
+ set_class_feature(acc, ARM_FEATURE_NEON);
+ set_class_feature(acc, ARM_FEATURE_GENERIC_TIMER);
+ set_class_feature(acc, ARM_FEATURE_AARCH64);
+ set_class_feature(acc, ARM_FEATURE_PMU);
+}
+
static void aarch64_host_object_init(Object *obj)
{
#if defined(CONFIG_KVM)
@@ -1122,8 +1137,12 @@ static bool aarch64_max_class_late_init(ARMCPUClass
*cpu, Error **errp)
return true;
}
- /* '-cpu max' for TCG: we currently do this as "A57 with extra things" */
+ /*
+ * '-cpu max' for TCG: we currently do this as "A57 with extra things"
+ * Retain the more generic dtb_compatible setting from host_class_init.
+ */
aarch64_a57_class_init(cpu);
+ cpu->dtb_compatible = "arm,arm-v8";
/*
* Reset MIDR so the guest doesn't mistake our 'max' CPU type for a real
@@ -1316,10 +1335,12 @@ static const ARMCPUInfo aarch64_cpus[] = {
.class_init = aarch64_a64fx_class_init,
.object_init = aarch64_a64fx_object_init },
{ .name = "max",
+ .class_init = aarch64_host_class_init,
.class_late_init = aarch64_max_class_late_init,
.object_init = aarch64_max_object_init },
#if defined(CONFIG_KVM) || defined(CONFIG_HVF)
{ .name = "host",
+ .class_init = aarch64_host_class_init,
.object_init = aarch64_host_object_init },
#endif
};
diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c
index 278a4b2ede..8bb8b475cd 100644
--- a/target/arm/hvf/hvf.c
+++ b/target/arm/hvf/hvf.c
@@ -97,10 +97,8 @@ static HVFVTimer vtimer;
typedef struct ARMHostCPUFeatures {
ARMISARegisters isar;
- uint64_t features;
uint64_t midr;
uint32_t reset_sctlr;
- const char *dtb_compatible;
} ARMHostCPUFeatures;
static ARMHostCPUFeatures arm_host_cpu_features;
@@ -489,13 +487,6 @@ static bool
hvf_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
hv_vcpu_exit_t *exit;
int i;
- ahcf->dtb_compatible = "arm,arm-v8";
- ahcf->features = (1ULL << ARM_FEATURE_V8) |
- (1ULL << ARM_FEATURE_NEON) |
- (1ULL << ARM_FEATURE_AARCH64) |
- (1ULL << ARM_FEATURE_PMU) |
- (1ULL << ARM_FEATURE_GENERIC_TIMER);
-
/* We set up a small vcpu to extract host registers */
if (hv_vcpu_create(&fd, &exit, NULL) != HV_SUCCESS) {
@@ -532,7 +523,7 @@ static bool
hvf_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
void hvf_arm_set_cpu_features_from_host(ARMCPU *cpu)
{
- if (!arm_host_cpu_features.dtb_compatible) {
+ if (!arm_host_cpu_features.reset_sctlr) {
if (!hvf_enabled() ||
!hvf_arm_get_host_cpu_features(&arm_host_cpu_features)) {
/*
@@ -544,9 +535,7 @@ void hvf_arm_set_cpu_features_from_host(ARMCPU *cpu)
}
}
- cpu->dtb_compatible = arm_host_cpu_features.dtb_compatible;
cpu->isar = arm_host_cpu_features.isar;
- cpu->env.features = arm_host_cpu_features.features;
cpu->midr = arm_host_cpu_features.midr;
cpu->reset_sctlr = arm_host_cpu_features.reset_sctlr;
}
diff --git a/target/arm/kvm.c b/target/arm/kvm.c
index 02a15c6013..ac164a6130 100644
--- a/target/arm/kvm.c
+++ b/target/arm/kvm.c
@@ -50,9 +50,7 @@ static bool cap_has_inject_ext_dabt;
*/
typedef struct ARMHostCPUFeatures {
ARMISARegisters isar;
- uint64_t features;
uint32_t target;
- const char *dtb_compatible;
} ARMHostCPUFeatures;
static ARMHostCPUFeatures arm_host_cpu_features;
@@ -1567,7 +1565,6 @@ static bool
kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
int fdarray[3];
bool sve_supported;
bool pmu_supported = false;
- uint64_t features = 0;
int err;
/* Old kernels may not know about the PREFERRED_TARGET ioctl: however
@@ -1615,7 +1612,6 @@ static bool
kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
}
ahcf->target = init.target;
- ahcf->dtb_compatible = "arm,arm-v8";
err = read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64pfr0,
ARM64_SYS_REG(3, 0, 0, 4, 0));
@@ -1760,31 +1756,12 @@ static bool
kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
kvm_arm_destroy_scratch_host_vcpu(fdarray);
- if (err < 0) {
- return false;
- }
-
- /*
- * We can assume any KVM supporting CPU is at least a v8
- * with VFPv4+Neon; this in turn implies most of the other
- * feature bits.
- */
- features |= 1ULL << ARM_FEATURE_V8;
- features |= 1ULL << ARM_FEATURE_NEON;
- features |= 1ULL << ARM_FEATURE_AARCH64;
- features |= 1ULL << ARM_FEATURE_PMU;
- features |= 1ULL << ARM_FEATURE_GENERIC_TIMER;
-
- ahcf->features = features;
-
- return true;
+ return !err;
}
void kvm_arm_set_cpu_features_from_host(ARMCPU *cpu)
{
- CPUARMState *env = &cpu->env;
-
- if (!arm_host_cpu_features.dtb_compatible) {
+ if (!arm_host_cpu_features.isar.id_aa64pfr0) {
if (!kvm_enabled() ||
!kvm_arm_get_host_cpu_features(&arm_host_cpu_features)) {
/* We can't report this error yet, so flag that we need to
@@ -1797,9 +1774,7 @@ void kvm_arm_set_cpu_features_from_host(ARMCPU *cpu)
}
cpu->kvm_target = arm_host_cpu_features.target;
- cpu->dtb_compatible = arm_host_cpu_features.dtb_compatible;
cpu->isar = arm_host_cpu_features.isar;
- env->features = arm_host_cpu_features.features;
}
/**
--
2.34.1
