On Mon, 2012-01-02 at 18:51 -0600, Anthony Liguori wrote: > This board never worked with TCG. It hasn't been updated since 0.13.0. I'm > fairly sure hardware doesn't exist anymore that you can run the KVM support > with.
It does exist, I have one :-) > So let's remove it. It can always be restored later if there is interest > again. Cheers, Ben. > Signed-off-by: Anthony Liguori <aligu...@us.ibm.com> > --- > Makefile.target | 3 +- > hw/ppc440.c | 106 --------------- > hw/ppc440.h | 21 --- > hw/ppc440_bamboo.c | 215 ----------------------------- > hw/ppc4xx_pci.c | 381 > ---------------------------------------------------- > hw/virtex_ml507.c | 1 - > 6 files changed, 1 insertions(+), 726 deletions(-) > delete mode 100644 hw/ppc440.c > delete mode 100644 hw/ppc440.h > delete mode 100644 hw/ppc440_bamboo.c > delete mode 100644 hw/ppc4xx_pci.c > > diff --git a/Makefile.target b/Makefile.target > index 3261383..b8ccf07 100644 > --- a/Makefile.target > +++ b/Makefile.target > @@ -246,8 +246,7 @@ obj-ppc-$(CONFIG_PSERIES) += spapr.o spapr_hcall.o > spapr_rtas.o spapr_vio.o > obj-ppc-$(CONFIG_PSERIES) += xics.o spapr_vty.o spapr_llan.o spapr_vscsi.o > obj-ppc-$(CONFIG_PSERIES) += spapr_pci.o device-hotplug.o pci-hotplug.o > # PowerPC 4xx boards > -obj-ppc-y += ppc4xx_devs.o ppc4xx_pci.o ppc405_uc.o ppc405_boards.o > -obj-ppc-y += ppc440.o ppc440_bamboo.o > +obj-ppc-y += ppc4xx_devs.o ppc405_uc.o ppc405_boards.o > # PowerPC E500 boards > obj-ppc-y += ppce500_mpc8544ds.o mpc8544_guts.o ppce500_spin.o > # PowerPC 440 Xilinx ML507 reference board. > diff --git a/hw/ppc440.c b/hw/ppc440.c > deleted file mode 100644 > index cd8a95d..0000000 > --- a/hw/ppc440.c > +++ /dev/null > @@ -1,106 +0,0 @@ > -/* > - * Qemu PowerPC 440 chip emulation > - * > - * Copyright 2007 IBM Corporation. > - * Authors: > - * Jerone Young <jyou...@us.ibm.com> > - * Christian Ehrhardt <ehrha...@linux.vnet.ibm.com> > - * Hollis Blanchard <holl...@us.ibm.com> > - * > - * This work is licensed under the GNU GPL license version 2 or later. > - * > - */ > - > -#include "hw.h" > -#include "pc.h" > -#include "isa.h" > -#include "ppc.h" > -#include "ppc4xx.h" > -#include "ppc440.h" > -#include "ppc405.h" > -#include "sysemu.h" > -#include "kvm.h" > - > -#define PPC440EP_PCI_CONFIG 0xeec00000 > -#define PPC440EP_PCI_INTACK 0xeed00000 > -#define PPC440EP_PCI_SPECIAL 0xeed00000 > -#define PPC440EP_PCI_REGS 0xef400000 > -#define PPC440EP_PCI_IO 0xe8000000 > -#define PPC440EP_PCI_IOLEN 0x00010000 > - > -#define PPC440EP_SDRAM_NR_BANKS 4 > - > -static const unsigned int ppc440ep_sdram_bank_sizes[] = { > - 256<<20, 128<<20, 64<<20, 32<<20, 16<<20, 8<<20, 0 > -}; > - > -CPUState *ppc440ep_init(MemoryRegion *address_space_mem, ram_addr_t > *ram_size, > - PCIBus **pcip, const unsigned int pci_irq_nrs[4], > - int do_init, const char *cpu_model) > -{ > - MemoryRegion *ram_memories > - = g_malloc(PPC440EP_SDRAM_NR_BANKS * sizeof(*ram_memories)); > - target_phys_addr_t ram_bases[PPC440EP_SDRAM_NR_BANKS]; > - target_phys_addr_t ram_sizes[PPC440EP_SDRAM_NR_BANKS]; > - CPUState *env; > - qemu_irq *pic; > - qemu_irq *irqs; > - qemu_irq *pci_irqs; > - > - if (cpu_model == NULL) { > - cpu_model = "440-Xilinx"; // XXX: should be 440EP > - } > - env = cpu_init(cpu_model); > - if (!env) { > - fprintf(stderr, "Unable to initialize CPU!\n"); > - exit(1); > - } > - > - ppc_dcr_init(env, NULL, NULL); > - > - /* interrupt controller */ > - irqs = g_malloc0(sizeof(qemu_irq) * PPCUIC_OUTPUT_NB); > - irqs[PPCUIC_OUTPUT_INT] = ((qemu_irq > *)env->irq_inputs)[PPC40x_INPUT_INT]; > - irqs[PPCUIC_OUTPUT_CINT] = ((qemu_irq > *)env->irq_inputs)[PPC40x_INPUT_CINT]; > - pic = ppcuic_init(env, irqs, 0x0C0, 0, 1); > - > - /* SDRAM controller */ > - memset(ram_bases, 0, sizeof(ram_bases)); > - memset(ram_sizes, 0, sizeof(ram_sizes)); > - *ram_size = ppc4xx_sdram_adjust(*ram_size, PPC440EP_SDRAM_NR_BANKS, > - ram_memories, > - ram_bases, ram_sizes, > - ppc440ep_sdram_bank_sizes); > - /* XXX 440EP's ECC interrupts are on UIC1, but we've only created UIC0. > */ > - ppc4xx_sdram_init(env, pic[14], PPC440EP_SDRAM_NR_BANKS, ram_memories, > - ram_bases, ram_sizes, do_init); > - > - /* PCI */ > - pci_irqs = g_malloc(sizeof(qemu_irq) * 4); > - pci_irqs[0] = pic[pci_irq_nrs[0]]; > - pci_irqs[1] = pic[pci_irq_nrs[1]]; > - pci_irqs[2] = pic[pci_irq_nrs[2]]; > - pci_irqs[3] = pic[pci_irq_nrs[3]]; > - *pcip = ppc4xx_pci_init(env, pci_irqs, > - PPC440EP_PCI_CONFIG, > - PPC440EP_PCI_INTACK, > - PPC440EP_PCI_SPECIAL, > - PPC440EP_PCI_REGS); > - if (!*pcip) > - printf("couldn't create PCI controller!\n"); > - > - isa_mmio_init(PPC440EP_PCI_IO, PPC440EP_PCI_IOLEN); > - > - if (serial_hds[0] != NULL) { > - serial_mm_init(address_space_mem, 0xef600300, 0, pic[0], > - PPC_SERIAL_MM_BAUDBASE, serial_hds[0], > - DEVICE_BIG_ENDIAN); > - } > - if (serial_hds[1] != NULL) { > - serial_mm_init(address_space_mem, 0xef600400, 0, pic[1], > - PPC_SERIAL_MM_BAUDBASE, serial_hds[1], > - DEVICE_BIG_ENDIAN); > - } > - > - return env; > -} > diff --git a/hw/ppc440.h b/hw/ppc440.h > deleted file mode 100644 > index 9c27c36..0000000 > --- a/hw/ppc440.h > +++ /dev/null > @@ -1,21 +0,0 @@ > -/* > - * Qemu PowerPC 440 board emualtion > - * > - * Copyright 2007 IBM Corporation. > - * Authors: Jerone Young <jyou...@us.ibm.com> > - * Christian Ehrhardt <ehrha...@linux.vnet.ibm.com> > - * > - * This work is licensed under the GNU GPL licence version 2 or later > - * > - */ > - > -#ifndef QEMU_PPC440_H > -#define QEMU_PPC440_H > - > -#include "hw.h" > - > -CPUState *ppc440ep_init(MemoryRegion *address_space, ram_addr_t *ram_size, > - PCIBus **pcip, const unsigned int pci_irq_nrs[4], > - int do_init, const char *cpu_model); > - > -#endif > diff --git a/hw/ppc440_bamboo.c b/hw/ppc440_bamboo.c > deleted file mode 100644 > index b734e3a..0000000 > --- a/hw/ppc440_bamboo.c > +++ /dev/null > @@ -1,215 +0,0 @@ > -/* > - * Qemu PowerPC 440 Bamboo board emulation > - * > - * Copyright 2007 IBM Corporation. > - * Authors: > - * Jerone Young <jyou...@us.ibm.com> > - * Christian Ehrhardt <ehrha...@linux.vnet.ibm.com> > - * Hollis Blanchard <holl...@us.ibm.com> > - * > - * This work is licensed under the GNU GPL license version 2 or later. > - * > - */ > - > -#include "config.h" > -#include "qemu-common.h" > -#include "net.h" > -#include "hw.h" > -#include "pci.h" > -#include "boards.h" > -#include "ppc440.h" > -#include "kvm.h" > -#include "kvm_ppc.h" > -#include "device_tree.h" > -#include "loader.h" > -#include "elf.h" > -#include "exec-memory.h" > - > -#define BINARY_DEVICE_TREE_FILE "bamboo.dtb" > - > -/* from u-boot */ > -#define KERNEL_ADDR 0x1000000 > -#define FDT_ADDR 0x1800000 > -#define RAMDISK_ADDR 0x1900000 > - > -static int bamboo_load_device_tree(target_phys_addr_t addr, > - uint32_t ramsize, > - target_phys_addr_t initrd_base, > - target_phys_addr_t initrd_size, > - const char *kernel_cmdline) > -{ > - int ret = -1; > -#ifdef CONFIG_FDT > - uint32_t mem_reg_property[] = { 0, 0, ramsize }; > - char *filename; > - int fdt_size; > - void *fdt; > - uint32_t tb_freq = 400000000; > - uint32_t clock_freq = 400000000; > - > - filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, BINARY_DEVICE_TREE_FILE); > - if (!filename) { > - goto out; > - } > - fdt = load_device_tree(filename, &fdt_size); > - g_free(filename); > - if (fdt == NULL) { > - goto out; > - } > - > - /* Manipulate device tree in memory. */ > - > - ret = qemu_devtree_setprop(fdt, "/memory", "reg", mem_reg_property, > - sizeof(mem_reg_property)); > - if (ret < 0) > - fprintf(stderr, "couldn't set /memory/reg\n"); > - > - ret = qemu_devtree_setprop_cell(fdt, "/chosen", "linux,initrd-start", > - initrd_base); > - if (ret < 0) > - fprintf(stderr, "couldn't set /chosen/linux,initrd-start\n"); > - > - ret = qemu_devtree_setprop_cell(fdt, "/chosen", "linux,initrd-end", > - (initrd_base + initrd_size)); > - if (ret < 0) > - fprintf(stderr, "couldn't set /chosen/linux,initrd-end\n"); > - > - ret = qemu_devtree_setprop_string(fdt, "/chosen", "bootargs", > - kernel_cmdline); > - if (ret < 0) > - fprintf(stderr, "couldn't set /chosen/bootargs\n"); > - > - /* Copy data from the host device tree into the guest. Since the guest > can > - * directly access the timebase without host involvement, we must expose > - * the correct frequencies. */ > - if (kvm_enabled()) { > - tb_freq = kvmppc_get_tbfreq(); > - clock_freq = kvmppc_get_clockfreq(); > - } > - > - qemu_devtree_setprop_cell(fdt, "/cpus/cpu@0", "clock-frequency", > - clock_freq); > - qemu_devtree_setprop_cell(fdt, "/cpus/cpu@0", "timebase-frequency", > - tb_freq); > - > - ret = rom_add_blob_fixed(BINARY_DEVICE_TREE_FILE, fdt, fdt_size, addr); > - g_free(fdt); > - > -out: > -#endif > - > - return ret; > -} > - > -static void bamboo_init(ram_addr_t ram_size, > - const char *boot_device, > - const char *kernel_filename, > - const char *kernel_cmdline, > - const char *initrd_filename, > - const char *cpu_model) > -{ > - unsigned int pci_irq_nrs[4] = { 28, 27, 26, 25 }; > - MemoryRegion *address_space_mem = get_system_memory(); > - PCIBus *pcibus; > - CPUState *env; > - uint64_t elf_entry; > - uint64_t elf_lowaddr; > - target_phys_addr_t entry = 0; > - target_phys_addr_t loadaddr = 0; > - target_long initrd_size = 0; > - int success; > - int i; > - > - /* Setup CPU. */ > - env = ppc440ep_init(address_space_mem, &ram_size, &pcibus, > - pci_irq_nrs, 1, cpu_model); > - > - if (pcibus) { > - /* Register network interfaces. */ > - for (i = 0; i < nb_nics; i++) { > - /* There are no PCI NICs on the Bamboo board, but there are > - * PCI slots, so we can pick whatever default model we want. */ > - pci_nic_init_nofail(&nd_table[i], "e1000", NULL); > - } > - } > - > - /* Load kernel. */ > - if (kernel_filename) { > - success = load_uimage(kernel_filename, &entry, &loadaddr, NULL); > - if (success < 0) { > - success = load_elf(kernel_filename, NULL, NULL, &elf_entry, > - &elf_lowaddr, NULL, 1, ELF_MACHINE, 0); > - entry = elf_entry; > - loadaddr = elf_lowaddr; > - } > - /* XXX try again as binary */ > - if (success < 0) { > - fprintf(stderr, "qemu: could not load kernel '%s'\n", > - kernel_filename); > - exit(1); > - } > - } > - > - /* Load initrd. */ > - if (initrd_filename) { > - initrd_size = load_image_targphys(initrd_filename, RAMDISK_ADDR, > - ram_size - RAMDISK_ADDR); > - > - if (initrd_size < 0) { > - fprintf(stderr, "qemu: could not load ram disk '%s' at %x\n", > - initrd_filename, RAMDISK_ADDR); > - exit(1); > - } > - } > - > - /* If we're loading a kernel directly, we must load the device tree too. > */ > - if (kernel_filename) { > - if (bamboo_load_device_tree(FDT_ADDR, ram_size, RAMDISK_ADDR, > - initrd_size, kernel_cmdline) < 0) { > - fprintf(stderr, "couldn't load device tree\n"); > - exit(1); > - } > - > - /* Set initial guest state. */ > - env->gpr[1] = (16<<20) - 8; > - env->gpr[3] = FDT_ADDR; > - env->nip = entry; > - /* XXX we currently depend on KVM to create some initial TLB > entries. */ > - } > - > - if (kvm_enabled()) > - kvmppc_init(); > -} > - > -static QEMUMachine bamboo_machine = { > - .name = "bamboo-0.13", > - .alias = "bamboo", > - .desc = "bamboo", > - .init = bamboo_init, > -}; > - > -static QEMUMachine bamboo_machine_v0_12 = { > - .name = "bamboo-0.12", > - .desc = "bamboo", > - .init = bamboo_init, > - .compat_props = (GlobalProperty[]) { > - { > - .driver = "virtio-serial-pci", > - .property = "max_ports", > - .value = stringify(1), > - },{ > - .driver = "virtio-serial-pci", > - .property = "vectors", > - .value = stringify(0), > - }, > - { /* end of list */ } > - }, > -}; > - > -static void bamboo_machine_init(void) > -{ > - qemu_register_machine(&bamboo_machine); > - qemu_register_machine(&bamboo_machine_v0_12); > -} > - > -machine_init(bamboo_machine_init); > diff --git a/hw/ppc4xx_pci.c b/hw/ppc4xx_pci.c > deleted file mode 100644 > index 2c69210..0000000 > --- a/hw/ppc4xx_pci.c > +++ /dev/null > @@ -1,381 +0,0 @@ > -/* > - * This program is free software; you can redistribute it and/or modify > - * it under the terms of the GNU General Public License, version 2, as > - * published by the Free Software Foundation. > - * > - * This program is distributed in the hope that it will be useful, > - * but WITHOUT ANY WARRANTY; without even the implied warranty of > - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > - * GNU General Public License for more details. > - * > - * You should have received a copy of the GNU General Public License > - * along with this program; if not, see <http://www.gnu.org/licenses/>. > - * > - * Copyright IBM Corp. 2008 > - * > - * Authors: Hollis Blanchard <holl...@us.ibm.com> > - */ > - > -/* This file implements emulation of the 32-bit PCI controller found in some > - * 4xx SoCs, such as the 440EP. */ > - > -#include "hw.h" > -#include "ppc.h" > -#include "ppc4xx.h" > -#include "pci.h" > -#include "pci_host.h" > -#include "exec-memory.h" > - > -#undef DEBUG > -#ifdef DEBUG > -#define DPRINTF(fmt, ...) do { printf(fmt, ## __VA_ARGS__); } while (0) > -#else > -#define DPRINTF(fmt, ...) > -#endif /* DEBUG */ > - > -struct PCIMasterMap { > - uint32_t la; > - uint32_t ma; > - uint32_t pcila; > - uint32_t pciha; > -}; > - > -struct PCITargetMap { > - uint32_t ms; > - uint32_t la; > -}; > - > -#define PPC4xx_PCI_NR_PMMS 3 > -#define PPC4xx_PCI_NR_PTMS 2 > - > -struct PPC4xxPCIState { > - struct PCIMasterMap pmm[PPC4xx_PCI_NR_PMMS]; > - struct PCITargetMap ptm[PPC4xx_PCI_NR_PTMS]; > - > - PCIHostState pci_state; > - PCIDevice *pci_dev; > - MemoryRegion iomem_addr; > - MemoryRegion iomem_regs; > -}; > -typedef struct PPC4xxPCIState PPC4xxPCIState; > - > -#define PCIC0_CFGADDR 0x0 > -#define PCIC0_CFGDATA 0x4 > - > -/* PLB Memory Map (PMM) registers specify which PLB addresses are translated > to > - * PCI accesses. */ > -#define PCIL0_PMM0LA 0x0 > -#define PCIL0_PMM0MA 0x4 > -#define PCIL0_PMM0PCILA 0x8 > -#define PCIL0_PMM0PCIHA 0xc > -#define PCIL0_PMM1LA 0x10 > -#define PCIL0_PMM1MA 0x14 > -#define PCIL0_PMM1PCILA 0x18 > -#define PCIL0_PMM1PCIHA 0x1c > -#define PCIL0_PMM2LA 0x20 > -#define PCIL0_PMM2MA 0x24 > -#define PCIL0_PMM2PCILA 0x28 > -#define PCIL0_PMM2PCIHA 0x2c > - > -/* PCI Target Map (PTM) registers specify which PCI addresses are translated > to > - * PLB accesses. */ > -#define PCIL0_PTM1MS 0x30 > -#define PCIL0_PTM1LA 0x34 > -#define PCIL0_PTM2MS 0x38 > -#define PCIL0_PTM2LA 0x3c > -#define PCI_REG_SIZE 0x40 > - > - > -static uint64_t pci4xx_cfgaddr_read(void *opaque, target_phys_addr_t addr, > - unsigned size) > -{ > - PPC4xxPCIState *ppc4xx_pci = opaque; > - > - return ppc4xx_pci->pci_state.config_reg; > -} > - > -static void pci4xx_cfgaddr_write(void *opaque, target_phys_addr_t addr, > - uint64_t value, unsigned size) > -{ > - PPC4xxPCIState *ppc4xx_pci = opaque; > - > - ppc4xx_pci->pci_state.config_reg = value & ~0x3; > -} > - > -static const MemoryRegionOps pci4xx_cfgaddr_ops = { > - .read = pci4xx_cfgaddr_read, > - .write = pci4xx_cfgaddr_write, > - .endianness = DEVICE_LITTLE_ENDIAN, > -}; > - > -static void ppc4xx_pci_reg_write4(void *opaque, target_phys_addr_t offset, > - uint64_t value, unsigned size) > -{ > - struct PPC4xxPCIState *pci = opaque; > - > - /* We ignore all target attempts at PCI configuration, effectively > - * assuming a bidirectional 1:1 mapping of PLB and PCI space. */ > - > - switch (offset) { > - case PCIL0_PMM0LA: > - pci->pmm[0].la = value; > - break; > - case PCIL0_PMM0MA: > - pci->pmm[0].ma = value; > - break; > - case PCIL0_PMM0PCIHA: > - pci->pmm[0].pciha = value; > - break; > - case PCIL0_PMM0PCILA: > - pci->pmm[0].pcila = value; > - break; > - > - case PCIL0_PMM1LA: > - pci->pmm[1].la = value; > - break; > - case PCIL0_PMM1MA: > - pci->pmm[1].ma = value; > - break; > - case PCIL0_PMM1PCIHA: > - pci->pmm[1].pciha = value; > - break; > - case PCIL0_PMM1PCILA: > - pci->pmm[1].pcila = value; > - break; > - > - case PCIL0_PMM2LA: > - pci->pmm[2].la = value; > - break; > - case PCIL0_PMM2MA: > - pci->pmm[2].ma = value; > - break; > - case PCIL0_PMM2PCIHA: > - pci->pmm[2].pciha = value; > - break; > - case PCIL0_PMM2PCILA: > - pci->pmm[2].pcila = value; > - break; > - > - case PCIL0_PTM1MS: > - pci->ptm[0].ms = value; > - break; > - case PCIL0_PTM1LA: > - pci->ptm[0].la = value; > - break; > - case PCIL0_PTM2MS: > - pci->ptm[1].ms = value; > - break; > - case PCIL0_PTM2LA: > - pci->ptm[1].la = value; > - break; > - > - default: > - printf("%s: unhandled PCI internal register 0x%lx\n", __func__, > - (unsigned long)offset); > - break; > - } > -} > - > -static uint64_t ppc4xx_pci_reg_read4(void *opaque, target_phys_addr_t offset, > - unsigned size) > -{ > - struct PPC4xxPCIState *pci = opaque; > - uint32_t value; > - > - switch (offset) { > - case PCIL0_PMM0LA: > - value = pci->pmm[0].la; > - break; > - case PCIL0_PMM0MA: > - value = pci->pmm[0].ma; > - break; > - case PCIL0_PMM0PCIHA: > - value = pci->pmm[0].pciha; > - break; > - case PCIL0_PMM0PCILA: > - value = pci->pmm[0].pcila; > - break; > - > - case PCIL0_PMM1LA: > - value = pci->pmm[1].la; > - break; > - case PCIL0_PMM1MA: > - value = pci->pmm[1].ma; > - break; > - case PCIL0_PMM1PCIHA: > - value = pci->pmm[1].pciha; > - break; > - case PCIL0_PMM1PCILA: > - value = pci->pmm[1].pcila; > - break; > - > - case PCIL0_PMM2LA: > - value = pci->pmm[2].la; > - break; > - case PCIL0_PMM2MA: > - value = pci->pmm[2].ma; > - break; > - case PCIL0_PMM2PCIHA: > - value = pci->pmm[2].pciha; > - break; > - case PCIL0_PMM2PCILA: > - value = pci->pmm[2].pcila; > - break; > - > - case PCIL0_PTM1MS: > - value = pci->ptm[0].ms; > - break; > - case PCIL0_PTM1LA: > - value = pci->ptm[0].la; > - break; > - case PCIL0_PTM2MS: > - value = pci->ptm[1].ms; > - break; > - case PCIL0_PTM2LA: > - value = pci->ptm[1].la; > - break; > - > - default: > - printf("%s: invalid PCI internal register 0x%lx\n", __func__, > - (unsigned long)offset); > - value = 0; > - } > - > - return value; > -} > - > -static const MemoryRegionOps pci_reg_ops = { > - .read = ppc4xx_pci_reg_read4, > - .write = ppc4xx_pci_reg_write4, > - .endianness = DEVICE_LITTLE_ENDIAN, > -}; > - > -static void ppc4xx_pci_reset(void *opaque) > -{ > - struct PPC4xxPCIState *pci = opaque; > - > - memset(pci->pmm, 0, sizeof(pci->pmm)); > - memset(pci->ptm, 0, sizeof(pci->ptm)); > -} > - > -/* On Bamboo, all pins from each slot are tied to a single board IRQ. This > - * may need further refactoring for other boards. */ > -static int ppc4xx_pci_map_irq(PCIDevice *pci_dev, int irq_num) > -{ > - int slot = pci_dev->devfn >> 3; > - > - DPRINTF("%s: devfn %x irq %d -> %d\n", __func__, > - pci_dev->devfn, irq_num, slot); > - > - return slot - 1; > -} > - > -static void ppc4xx_pci_set_irq(void *opaque, int irq_num, int level) > -{ > - qemu_irq *pci_irqs = opaque; > - > - DPRINTF("%s: PCI irq %d\n", __func__, irq_num); > - qemu_set_irq(pci_irqs[irq_num], level); > -} > - > -static const VMStateDescription vmstate_pci_master_map = { > - .name = "pci_master_map", > - .version_id = 0, > - .minimum_version_id = 0, > - .minimum_version_id_old = 0, > - .fields = (VMStateField[]) { > - VMSTATE_UINT32(la, struct PCIMasterMap), > - VMSTATE_UINT32(ma, struct PCIMasterMap), > - VMSTATE_UINT32(pcila, struct PCIMasterMap), > - VMSTATE_UINT32(pciha, struct PCIMasterMap), > - VMSTATE_END_OF_LIST() > - } > -}; > - > -static const VMStateDescription vmstate_pci_target_map = { > - .name = "pci_target_map", > - .version_id = 0, > - .minimum_version_id = 0, > - .minimum_version_id_old = 0, > - .fields = (VMStateField[]) { > - VMSTATE_UINT32(ms, struct PCITargetMap), > - VMSTATE_UINT32(la, struct PCITargetMap), > - VMSTATE_END_OF_LIST() > - } > -}; > - > -static const VMStateDescription vmstate_ppc4xx_pci = { > - .name = "ppc4xx_pci", > - .version_id = 1, > - .minimum_version_id = 1, > - .minimum_version_id_old = 1, > - .fields = (VMStateField[]) { > - VMSTATE_PCI_DEVICE_POINTER(pci_dev, PPC4xxPCIState), > - VMSTATE_STRUCT_ARRAY(pmm, PPC4xxPCIState, PPC4xx_PCI_NR_PMMS, 1, > - vmstate_pci_master_map, > - struct PCIMasterMap), > - VMSTATE_STRUCT_ARRAY(ptm, PPC4xxPCIState, PPC4xx_PCI_NR_PTMS, 1, > - vmstate_pci_target_map, > - struct PCITargetMap), > - VMSTATE_END_OF_LIST() > - } > -}; > - > -/* XXX Interrupt acknowledge cycles not supported. */ > -PCIBus *ppc4xx_pci_init(CPUState *env, qemu_irq pci_irqs[4], > - target_phys_addr_t config_space, > - target_phys_addr_t int_ack, > - target_phys_addr_t special_cycle, > - target_phys_addr_t registers) > -{ > - PPC4xxPCIState *controller; > - static int ppc4xx_pci_id; > - uint8_t *pci_conf; > - > - controller = g_malloc0(sizeof(PPC4xxPCIState)); > - > - controller->pci_state.bus = pci_register_bus(NULL, "pci", > - ppc4xx_pci_set_irq, > - ppc4xx_pci_map_irq, > - pci_irqs, > - get_system_memory(), > - get_system_io(), > - 0, 4); > - > - controller->pci_dev = pci_register_device(controller->pci_state.bus, > - "host bridge", > sizeof(PCIDevice), > - 0, NULL, NULL); > - pci_conf = controller->pci_dev->config; > - pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_IBM); > - pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_IBM_440GX); > - pci_config_set_class(pci_conf, PCI_CLASS_BRIDGE_OTHER); > - > - /* CFGADDR */ > - memory_region_init_io(&controller->iomem_addr, &pci4xx_cfgaddr_ops, > - controller, "pci.cfgaddr", 4); > - memory_region_add_subregion(get_system_memory(), > - config_space + PCIC0_CFGADDR, > - &controller->iomem_addr); > - > - /* CFGDATA */ > - memory_region_init_io(&controller->pci_state.data_mem, > - &pci_host_data_be_ops, > - &controller->pci_state, "pci-conf-data", 4); > - memory_region_add_subregion(get_system_memory(), > - config_space + PCIC0_CFGDATA, > - &controller->pci_state.data_mem); > - > - /* Internal registers */ > - memory_region_init_io(&controller->iomem_regs, &pci_reg_ops, controller, > - "pci.regs", PCI_REG_SIZE); > - memory_region_add_subregion(get_system_memory(), registers, > - &controller->iomem_regs); > - > - qemu_register_reset(ppc4xx_pci_reset, controller); > - > - /* XXX load/save code not tested. */ > - vmstate_register(&controller->pci_dev->qdev, ppc4xx_pci_id++, > - &vmstate_ppc4xx_pci, controller); > - > - return controller->pci_state.bus; > -} > diff --git a/hw/virtex_ml507.c b/hw/virtex_ml507.c > index 6ffb896..1dc8a8f 100644 > --- a/hw/virtex_ml507.c > +++ b/hw/virtex_ml507.c > @@ -38,7 +38,6 @@ > > #include "ppc.h" > #include "ppc4xx.h" > -#include "ppc440.h" > #include "ppc405.h" > > #include "blockdev.h"