On Wed, Jan 11, 2023 at 4:17 AM Daniel Henrique Barboza <dbarb...@ventanamicro.com> wrote: > > There is an informal contract between the cpu_init() functions and > riscv_cpu_realize(): if cpu->env.misa_ext is zero, assume that the > default settings were loaded via register_cpu_props() and do validations > to set env.misa_ext. If it's not zero, skip this whole process and > assume that the board somehow did everything. > > At this moment, all SiFive CPUs are setting a non-zero misa_ext during > their cpu_init() and skipping a good chunk of riscv_cpu_realize(). > This causes problems when the code being skipped in riscv_cpu_realize() > contains fixes or assumptions that affects all CPUs, meaning that SiFive > CPUs are missing out. > > To allow this code to not be skipped anymore, all the cpu->cfg.ext_* > attributes > needs to be set during cpu_init() time. At this moment this is being done in > register_cpu_props(). The SiFive oards are setting their own extensions during
The SiFive boards > cpu_init() though, meaning that they don't want all the defaults from > register_cpu_props(). > > Let's move the contract between *_cpu_init() and riscv_cpu_realize() to > register_cpu_props(). Inside this function we'll check if cpu->env.misa_ext > was set and, if that's the case, set all relevant cpu->cfg.ext_* > attributes, and only that. Leave the 'misa_ext' = 0 case as is today, > i.e. loading all the defaults from riscv_cpu_extensions[]. > > register_cpu_props() can then be called by all the cpu_init() functions, > including the SiFive ones. This will make all CPUs behave more in line > with that riscv_cpu_realize() expects. with what > > Signed-off-by: Daniel Henrique Barboza <dbarb...@ventanamicro.com> > --- > target/riscv/cpu.c | 40 ++++++++++++++++++++++++++++++++++++++++ > target/riscv/cpu.h | 4 ++++ > 2 files changed, 44 insertions(+) > Regards, Bin