On 24 January 2012 07:59, Andreas Färber <afaer...@suse.de> wrote: > Am 13.01.2012 21:52, schrieb Peter Maydell: >> @@ -433,6 +433,7 @@ void cpu_arm_set_cp_io(CPUARMState *env, int cpnum, >> #define ARM_CPUID_CORTEXA8 0x410fc080 >> #define ARM_CPUID_CORTEXA9 0x410fc090 >> #define ARM_CPUID_CORTEXM3 0x410fc231 >> +#define ARM_CPUID_CORTEXA15 0x412fc0f1 > > Reminder of our rnpn topic...
Yeah. I have a cp15-rework series brewing that might assist here. > We don't seem to have a clear ordering system but I'd suggest to move > A15 one line up, to group the As and Ms in ascending order respectively. Good idea. >> @@ -413,6 +444,7 @@ static const struct arm_cpu_t arm_cpu_names[] = { >> { ARM_CPUID_CORTEXM3, "cortex-m3"}, >> { ARM_CPUID_CORTEXA8, "cortex-a8"}, >> { ARM_CPUID_CORTEXA9, "cortex-a9"}, >> + { ARM_CPUID_CORTEXA15, "cortex-a15"}, > > Space please. OK. (I just copy-pasted the a9 line, as you've probably guessed.) >> + case 2: >> + /* L2 cache auxiliary control (A8) or control (A15) */ >> + if (ARM_CPUID(env) == ARM_CPUID_CORTEXA15) { > > Change of mind? You opposed uses of ARM_CPUID() for Cortex-R4F. I kind of view this as a small interim bodge. My aim with my cp15 rework is that instead of all these switches we will just set up the cp15 registers for the CPU at cpu_init time, so A15 will set up one thing, A8 something else and A9 et al set up nothing at all [and so get the default UNDEF behaviour]. If you can fish the particular mail of mine you have in mind out of the archives I can reread it and see if I disagree with myself :-) -- PMM