W dniu 13.03.2023 o 04:39, Chen Baozi pisze:
Add implementation defined registers for neoverse-n1 which
would be accessed by TF-A. Since there is no DSU in Qemu,
CPUCFR_EL1.SCU bit is set to 1 to avoid DSU registers definition.
Signed-off-by: Chen Baozi<chenba...@phytium.com.cn>
Tested-by: Marcin Juszkiewicz <marcin.juszkiew...@linaro.org>
~ # cat /proc/cpuinfo
processor : 0
BogoMIPS : 125.00
Features : fp asimd evtstrm aes pmull sha1 sha2 crc32 atomics
fphp asimdhp cpuid asimdrdm lrcpc dcpop asimddp ssbs
CPU implementer : 0x41
CPU architecture: 8
CPU variant : 0x4
CPU part : 0xd0c
CPU revision : 1
