On Mon, 13 Mar 2023 at 03:39, Chen Baozi <chenba...@phytium.com.cn> wrote: > > Add implementation defined registers for neoverse-n1 which > would be accessed by TF-A. Since there is no DSU in Qemu, > CPUCFR_EL1.SCU bit is set to 1 to avoid DSU registers definition. > > Signed-off-by: Chen Baozi <chenba...@phytium.com.cn> > --- > target/arm/cpu64.c | 69 ++++++++++++++++++++++++++++++++++++++++++++++ > 1 file changed, 69 insertions(+) >
Applied to target-arm.next, thanks. -- PMM
