On Wed, 5 Apr 2023 15:57:38 +0530 Raghu H <raghuhac...@gmail.com> wrote: Hi Raghu,
Thanks for tidying this up! (and reporting it in the first place) A few minor comments for v2. A better title might be docs/cxl: Remove incorrect CXL type 3 size parameter. > cxl device typ3 size is read from the memory backend device, removing the cxl-type3 memory size is read directly from the provided memory backed end device. Remove non existent size option. > size option specified in cxl sample command. > > Updating sample command to reflect target architecture as x86_64. There are two changes in here. Please split it into two patches and add a minimal cover letter (mostly as it gives a place for people to respond to both of them with tags etc). > > Signed-off-by: Raghu H <raghuhac...@gmail.com> > --- > docs/system/devices/cxl.rst | 14 +++++++------- > 1 file changed, 7 insertions(+), 7 deletions(-) > > diff --git a/docs/system/devices/cxl.rst b/docs/system/devices/cxl.rst > index f25783a4ec..b228146cec 100644 > --- a/docs/system/devices/cxl.rst > +++ b/docs/system/devices/cxl.rst > @@ -302,7 +302,7 @@ Example command lines > --------------------- > A very simple setup with just one directly attached CXL Type 3 device:: > > - qemu-system-aarch64 -M virt,gic-version=3,cxl=on -m 4g,maxmem=8G,slots=8 > -cpu max \ > + qemu-system-x86_64 -m 4G,slots=8,maxmem=8G -smp 4 -machine > type=q35,accel=kvm,nvdimm=on,cxl=on -enable-kvm \ Minimize the change (and definitely don't tell people to use kvm as that's broken for some usecases - instructions in CXL memory). + qemu-system-x86_64 -M q35,cxl=on -m 4G,maxmem=8G,slots=8 \ is probably the right combination (I tidied up the g / G mix whilst touching the line. > ... > -object > memory-backend-file,id=cxl-mem1,share=on,mem-path=/tmp/cxltest.raw,size=256M \ > -object > memory-backend-file,id=cxl-lsa1,share=on,mem-path=/tmp/lsa.raw,size=256M \ > @@ -315,7 +315,7 @@ A setup suitable for 4 way interleave. Only one fixed > window provided, to enable > interleave across 2 CXL host bridges. Each host bridge has 2 CXL Root > Ports, with > the CXL Type3 device directly attached (no switches).:: > > - qemu-system-aarch64 -M virt,gic-version=3,cxl=on -m 4g,maxmem=8G,slots=8 > -cpu max \ > + qemu-system-x86_64 -m 4G,slots=8,maxmem=8G -smp 4 -machine > type=q35,accel=kvm,nvdimm=on,cxl=on -enable-kvm \ > ... > -object > memory-backend-file,id=cxl-mem1,share=on,mem-path=/tmp/cxltest.raw,size=256M \ > -object > memory-backend-file,id=cxl-mem2,share=on,mem-path=/tmp/cxltest2.raw,size=256M > \ > @@ -339,7 +339,7 @@ the CXL Type3 device directly attached (no switches).:: > > An example of 4 devices below a switch suitable for 1, 2 or 4 way > interleave:: > > - qemu-system-aarch64 -M virt,gic-version=3,cxl=on -m 4g,maxmem=8G,slots=8 > -cpu max \ > + qemu-system-x86_64 -m 4G,slots=8,maxmem=8G -smp 4 -machine > type=q35,accel=kvm,nvdimm=on,cxl=on -enable-kvm \ > ... > -object > memory-backend-file,id=cxl-mem0,share=on,mem-path=/tmp/cxltest.raw,size=256M \ > -object > memory-backend-file,id=cxl-mem1,share=on,mem-path=/tmp/cxltest1.raw,size=256M > \ > @@ -354,13 +354,13 @@ An example of 4 devices below a switch suitable for 1, > 2 or 4 way interleave:: > -device cxl-rp,port=1,bus=cxl.1,id=root_port1,chassis=0,slot=1 \ > -device cxl-upstream,bus=root_port0,id=us0 \ > -device cxl-downstream,port=0,bus=us0,id=swport0,chassis=0,slot=4 \ > - -device > cxl-type3,bus=swport0,memdev=cxl-mem0,lsa=cxl-lsa0,id=cxl-pmem0,size=256M \ > + -device cxl-type3,bus=swport0,memdev=cxl-mem0,lsa=cxl-lsa0,id=cxl-pmem0 \ > -device cxl-downstream,port=1,bus=us0,id=swport1,chassis=0,slot=5 \ > - -device > cxl-type3,bus=swport1,memdev=cxl-mem1,lsa=cxl-lsa1,id=cxl-pmem1,size=256M \ > + -device cxl-type3,bus=swport1,memdev=cxl-mem1,lsa=cxl-lsa1,id=cxl-pmem1 \ > -device cxl-downstream,port=2,bus=us0,id=swport2,chassis=0,slot=6 \ > - -device > cxl-type3,bus=swport2,memdev=cxl-mem2,lsa=cxl-lsa2,id=cxl-pmem2,size=256M \ > + -device cxl-type3,bus=swport2,memdev=cxl-mem2,lsa=cxl-lsa2,id=cxl-pmem2 \ > -device cxl-downstream,port=3,bus=us0,id=swport3,chassis=0,slot=7 \ > - -device > cxl-type3,bus=swport3,memdev=cxl-mem3,lsa=cxl-lsa3,id=cxl-pmem3,size=256M \ > + -device cxl-type3,bus=swport3,memdev=cxl-mem3,lsa=cxl-lsa3,id=cxl-pmem3 \ > -M > cxl-fmw.0.targets.0=cxl.1,cxl-fmw.0.size=4G,cxl-fmw.0.interleave-granularity=4k > > Kernel Configuration Options
