Hi, this patch series tries to properly implement privilege levels for the TriCore, as discussed in https://lore.kernel.org/qemu-devel/20230118090319.32n4uto7ogy3gfr6@schnipp.zuhause/.
While implementing privilege traps for the SV/UM1 only insns, I saw that the RESTORE insn uses the wrong ICR.IE bit. So I fixed that as well. Cheers, Bastian Bastian Koppelmann (4): target/tricore: Introduce priv tb flag target/tricore: Implement privilege level for all insns target/tricore: Honour privilege changes on PSW write target/tricore: Fix ICR.IE offset in RESTORE insn target/tricore/cpu.h | 17 +++++++---- target/tricore/op_helper.c | 11 +++++++ target/tricore/translate.c | 61 ++++++++++++++++++++++++++++---------- 3 files changed, 68 insertions(+), 21 deletions(-) -- 2.40.1
