On 6/14/23 18:59, Bastian Koppelmann wrote:
from ISA v1.6.1 onwards the bit position of ICR.IE changed.
ctx->icr_ie_offset contains the correct value for the ISA version used
by the vCPU.
Signed-off-by: Bastian Koppelmann <kbast...@mail.uni-paderborn.de>
---
target/tricore/translate.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/target/tricore/translate.c b/target/tricore/translate.c
index baf13fc205..e4e57130bf 100644
--- a/target/tricore/translate.c
+++ b/target/tricore/translate.c
@@ -7959,7 +7959,8 @@ static void decode_sys_interrupts(DisasContext *ctx)
case OPC2_32_SYS_RESTORE:
if (has_feature(ctx, TRICORE_FEATURE_16)) {
if (ctx->priv == TRICORE_PRIV_SM || ctx->priv ==
TRICORE_PRIV_UM1) {
- tcg_gen_deposit_tl(cpu_ICR, cpu_ICR, cpu_gpr_d[r1], 8, 1);
+ tcg_gen_deposit_tl(cpu_ICR, cpu_ICR, cpu_gpr_d[r1],
+ ctx->icr_ie_offset, 1);
} else {
generate_trap(ctx, TRAPC_PROT, TIN1_PRIV);
}
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Additionally, you need to exit to the main loop, so that exceptions may be recognized
after re-enabling interrupts. This is missing from ENABLE as well.
r~
