On 7/10/23 13:31, Alistair Francis wrote:
The following changes since commit fcb237e64f9d026c03d635579c7b288d0008a6e5:
Merge tag 'pull-vfio-20230710' ofhttps://github.com/legoater/qemu into
staging (2023-07-10 09:17:06 +0100)
are available in the Git repository at:
https://github.com/alistair23/qemu.git tags/pull-riscv-to-apply-20230710-1
for you to fetch changes up to a47842d16653b4f73b5d56ff0c252dd8a329481b:
riscv: Add support for the Zfa extension (2023-07-10 22:29:20 +1000)
----------------------------------------------------------------
Third RISC-V PR for 8.1
* Use xl instead of mxl for disassemble
* Factor out extension tests to cpu_cfg.h
* disas/riscv: Add vendor extension support
* disas/riscv: Add support for XVentanaCondOps
* disas/riscv: Add support for XThead* instructions
* Fix mstatus related problems
* Fix veyron-v1 CPU properties
* Fix the xlen for data address when MPRV=1
* opensbi: Upgrade from v1.2 to v1.3
* Enable 32-bit Spike OpenSBI boot testing
* Support the watchdog timer of HiFive 1 rev b
* Only build qemu-system-riscv$$ on rv$$ host
* Add RVV registers to log
* Restrict ACLINT to TCG
* Add syscall riscv_hwprobe
* Add support for BF16 extensions
* KVM_RISCV_SET_TIMER macro is not configured correctly
* Generate devicetree only after machine initialization is complete
* virt: Convert fdt_load_addr to uint64_t
* KVM: fixes and enhancements
* Add support for the Zfa extension
Applied, thanks. Please update https://wiki.qemu.org/ChangeLog/8.1 as
appropriate.
r~
