On Wed, Sep 20, 2023 at 10:58 PM Daniel Henrique Barboza
<dbarb...@ventanamicro.com> wrote:
>
> All code related to MISA TCG properties is also moved.
>
> At this point, all TCG properties handling is done in tcg-cpu.c, all KVM
> properties handling is done in kvm-cpu.c.
>
> Signed-off-by: Daniel Henrique Barboza <dbarb...@ventanamicro.com>
> Reviewed-by: Andrew Jones <ajo...@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.fran...@wdc.com>
Alistair
> ---
> target/riscv/cpu.c | 90 --------------------------------------
> target/riscv/cpu.h | 1 -
> target/riscv/tcg/tcg-cpu.c | 90 ++++++++++++++++++++++++++++++++++++++
> 3 files changed, 90 insertions(+), 91 deletions(-)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 4875feded7..46263e55d5 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -1211,47 +1211,6 @@ static void riscv_cpu_init(Object *obj)
> #endif /* CONFIG_USER_ONLY */
> }
>
> -typedef struct RISCVCPUMisaExtConfig {
> - target_ulong misa_bit;
> - bool enabled;
> -} RISCVCPUMisaExtConfig;
> -
> -static void cpu_set_misa_ext_cfg(Object *obj, Visitor *v, const char *name,
> - void *opaque, Error **errp)
> -{
> - const RISCVCPUMisaExtConfig *misa_ext_cfg = opaque;
> - target_ulong misa_bit = misa_ext_cfg->misa_bit;
> - RISCVCPU *cpu = RISCV_CPU(obj);
> - CPURISCVState *env = &cpu->env;
> - bool value;
> -
> - if (!visit_type_bool(v, name, &value, errp)) {
> - return;
> - }
> -
> - if (value) {
> - env->misa_ext |= misa_bit;
> - env->misa_ext_mask |= misa_bit;
> - } else {
> - env->misa_ext &= ~misa_bit;
> - env->misa_ext_mask &= ~misa_bit;
> - }
> -}
> -
> -static void cpu_get_misa_ext_cfg(Object *obj, Visitor *v, const char *name,
> - void *opaque, Error **errp)
> -{
> - const RISCVCPUMisaExtConfig *misa_ext_cfg = opaque;
> - target_ulong misa_bit = misa_ext_cfg->misa_bit;
> - RISCVCPU *cpu = RISCV_CPU(obj);
> - CPURISCVState *env = &cpu->env;
> - bool value;
> -
> - value = env->misa_ext & misa_bit;
> -
> - visit_type_bool(v, name, &value, errp);
> -}
> -
> typedef struct misa_ext_info {
> const char *name;
> const char *description;
> @@ -1312,55 +1271,6 @@ const char *riscv_get_misa_ext_description(uint32_t
> bit)
> return val;
> }
>
> -#define MISA_CFG(_bit, _enabled) \
> - {.misa_bit = _bit, .enabled = _enabled}
> -
> -static const RISCVCPUMisaExtConfig misa_ext_cfgs[] = {
> - MISA_CFG(RVA, true),
> - MISA_CFG(RVC, true),
> - MISA_CFG(RVD, true),
> - MISA_CFG(RVF, true),
> - MISA_CFG(RVI, true),
> - MISA_CFG(RVE, false),
> - MISA_CFG(RVM, true),
> - MISA_CFG(RVS, true),
> - MISA_CFG(RVU, true),
> - MISA_CFG(RVH, true),
> - MISA_CFG(RVJ, false),
> - MISA_CFG(RVV, false),
> - MISA_CFG(RVG, false),
> -};
> -
> -/*
> - * We do not support user choice tracking for MISA
> - * extensions yet because, so far, we do not silently
> - * change MISA bits during realize() (RVG enables MISA
> - * bits but the user is warned about it).
> - */
> -void riscv_cpu_add_misa_properties(Object *cpu_obj)
> -{
> - int i;
> -
> - for (i = 0; i < ARRAY_SIZE(misa_ext_cfgs); i++) {
> - const RISCVCPUMisaExtConfig *misa_cfg = &misa_ext_cfgs[i];
> - int bit = misa_cfg->misa_bit;
> - const char *name = riscv_get_misa_ext_name(bit);
> - const char *desc = riscv_get_misa_ext_description(bit);
> -
> - /* Check if KVM already created the property */
> - if (object_property_find(cpu_obj, name)) {
> - continue;
> - }
> -
> - object_property_add(cpu_obj, name, "bool",
> - cpu_get_misa_ext_cfg,
> - cpu_set_misa_ext_cfg,
> - NULL, (void *)misa_cfg);
> - object_property_set_description(cpu_obj, name, desc);
> - object_property_set_bool(cpu_obj, name, misa_cfg->enabled, NULL);
> - }
> -}
> -
> #define MULTI_EXT_CFG_BOOL(_name, _prop, _defval) \
> {.name = _name, .offset = CPU_CFG_OFFSET(_prop), \
> .enabled = _defval}
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index 01cbcbe119..aba8192c74 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -726,7 +726,6 @@ extern const RISCVCPUMultiExtConfig
> riscv_cpu_vendor_exts[];
> extern const RISCVCPUMultiExtConfig riscv_cpu_experimental_exts[];
> extern Property riscv_cpu_options[];
>
> -void riscv_cpu_add_misa_properties(Object *cpu_obj);
> void riscv_add_satp_mode_properties(Object *obj);
>
> /* CSR function table */
> diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
> index 5d71ff2cce..c326ab37a2 100644
> --- a/target/riscv/tcg/tcg-cpu.c
> +++ b/target/riscv/tcg/tcg-cpu.c
> @@ -580,6 +580,96 @@ static bool tcg_cpu_realizefn(CPUState *cs, Error **errp)
> return true;
> }
>
> +typedef struct RISCVCPUMisaExtConfig {
> + target_ulong misa_bit;
> + bool enabled;
> +} RISCVCPUMisaExtConfig;
> +
> +static void cpu_set_misa_ext_cfg(Object *obj, Visitor *v, const char *name,
> + void *opaque, Error **errp)
> +{
> + const RISCVCPUMisaExtConfig *misa_ext_cfg = opaque;
> + target_ulong misa_bit = misa_ext_cfg->misa_bit;
> + RISCVCPU *cpu = RISCV_CPU(obj);
> + CPURISCVState *env = &cpu->env;
> + bool value;
> +
> + if (!visit_type_bool(v, name, &value, errp)) {
> + return;
> + }
> +
> + if (value) {
> + env->misa_ext |= misa_bit;
> + env->misa_ext_mask |= misa_bit;
> + } else {
> + env->misa_ext &= ~misa_bit;
> + env->misa_ext_mask &= ~misa_bit;
> + }
> +}
> +
> +static void cpu_get_misa_ext_cfg(Object *obj, Visitor *v, const char *name,
> + void *opaque, Error **errp)
> +{
> + const RISCVCPUMisaExtConfig *misa_ext_cfg = opaque;
> + target_ulong misa_bit = misa_ext_cfg->misa_bit;
> + RISCVCPU *cpu = RISCV_CPU(obj);
> + CPURISCVState *env = &cpu->env;
> + bool value;
> +
> + value = env->misa_ext & misa_bit;
> +
> + visit_type_bool(v, name, &value, errp);
> +}
> +
> +#define MISA_CFG(_bit, _enabled) \
> + {.misa_bit = _bit, .enabled = _enabled}
> +
> +static const RISCVCPUMisaExtConfig misa_ext_cfgs[] = {
> + MISA_CFG(RVA, true),
> + MISA_CFG(RVC, true),
> + MISA_CFG(RVD, true),
> + MISA_CFG(RVF, true),
> + MISA_CFG(RVI, true),
> + MISA_CFG(RVE, false),
> + MISA_CFG(RVM, true),
> + MISA_CFG(RVS, true),
> + MISA_CFG(RVU, true),
> + MISA_CFG(RVH, true),
> + MISA_CFG(RVJ, false),
> + MISA_CFG(RVV, false),
> + MISA_CFG(RVG, false),
> +};
> +
> +/*
> + * We do not support user choice tracking for MISA
> + * extensions yet because, so far, we do not silently
> + * change MISA bits during realize() (RVG enables MISA
> + * bits but the user is warned about it).
> + */
> +static void riscv_cpu_add_misa_properties(Object *cpu_obj)
> +{
> + int i;
> +
> + for (i = 0; i < ARRAY_SIZE(misa_ext_cfgs); i++) {
> + const RISCVCPUMisaExtConfig *misa_cfg = &misa_ext_cfgs[i];
> + int bit = misa_cfg->misa_bit;
> + const char *name = riscv_get_misa_ext_name(bit);
> + const char *desc = riscv_get_misa_ext_description(bit);
> +
> + /* Check if KVM already created the property */
> + if (object_property_find(cpu_obj, name)) {
> + continue;
> + }
> +
> + object_property_add(cpu_obj, name, "bool",
> + cpu_get_misa_ext_cfg,
> + cpu_set_misa_ext_cfg,
> + NULL, (void *)misa_cfg);
> + object_property_set_description(cpu_obj, name, desc);
> + object_property_set_bool(cpu_obj, name, misa_cfg->enabled, NULL);
> + }
> +}
> +
> static void cpu_set_multi_ext_cfg(Object *obj, Visitor *v, const char *name,
> void *opaque, Error **errp)
> {
> --
> 2.41.0
>
>
