Re: [PATCH] MAINTAINERS: Add unowned RISC-V related files to the right sections

[LIU Zhiwei]

On 2023/9/29 20:37, Thomas Huth wrote:

There are a bunch of RISC-V files that are currently not covered
by the "get_maintainers.pl" script. Add them to the right sections
in MAINTAINERS to fix this problem.

Signed-off-by: Thomas Huth <th...@redhat.com>

Reviewed-by: LIU Zhiwei <zhiwei_...@linux.alibaba.com>

Zhiwei

---
  MAINTAINERS | 10 +++++++++-
  1 file changed, 9 insertions(+), 1 deletion(-)

diff --git a/MAINTAINERS b/MAINTAINERS
index 355b1960ce..1313257180 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -317,8 +317,11 @@ R: Daniel Henrique Barboza <dbarb...@ventanamicro.com>
  R: Liu Zhiwei <zhiwei_...@linux.alibaba.com>
  L: qemu-ri...@nongnu.org
  S: Supported
+F: configs/targets/riscv*
+F: docs/system/target-riscv.rst
  F: target/riscv/
  F: hw/riscv/
+F: hw/intc/riscv*
  F: include/hw/riscv/
  F: linux-user/host/riscv32/
  F: linux-user/host/riscv64/
@@ -330,6 +333,7 @@ L: qemu-ri...@nongnu.org
  S: Supported
  F: target/riscv/insn_trans/trans_xthead.c.inc
  F: target/riscv/xthead*.decode
+F: disas/riscv-xthead*

RISC-V XVentanaCondOps extension

  M: Philipp Tomsich <philipp.toms...@vrull.eu>
@@ -337,6 +341,7 @@ L: qemu-ri...@nongnu.org
  S: Maintained
  F: target/riscv/XVentanaCondOps.decode
  F: target/riscv/insn_trans/trans_xventanacondops.c.inc
+F: disas/riscv-xventana*

RENESAS RX CPUs

  R: Yoshinori Sato <ys...@users.sourceforge.jp>
@@ -1518,6 +1523,7 @@ Microchip PolarFire SoC Icicle Kit
  M: Bin Meng <bin.m...@windriver.com>
  L: qemu-ri...@nongnu.org
  S: Supported
+F: docs/system/riscv/microchip-icicle-kit.rst
  F: hw/riscv/microchip_pfsoc.c
  F: hw/char/mchp_pfsoc_mmuart.c
  F: hw/misc/mchp_pfsoc_dmc.c
@@ -1533,6 +1539,7 @@ Shakti C class SoC
  M: Vijai Kumar K <vi...@behindbytes.com>
  L: qemu-ri...@nongnu.org
  S: Supported
+F: docs/system/riscv/shakti-c.rst
  F: hw/riscv/shakti_c.c
  F: hw/char/shakti_uart.c
  F: include/hw/riscv/shakti_c.h
@@ -1544,6 +1551,7 @@ M: Bin Meng <bin.m...@windriver.com>
  M: Palmer Dabbelt <pal...@dabbelt.com>
  L: qemu-ri...@nongnu.org
  S: Supported
+F: docs/system/riscv/sifive_u.rst
  F: hw/*/*sifive*.c
  F: include/hw/*/*sifive*.h

@@ -3543,7 +3551,7 @@ M: Alistair Francis <alistair.fran...@wdc.com>

  L: qemu-ri...@nongnu.org
  S: Maintained
  F: tcg/riscv/
-F: disas/riscv.c
+F: disas/riscv.[ch]

S390 TCG target

  M: Richard Henderson <richard.hender...@linaro.org>