On Wed, 11 Oct 2023 20:43:51 +0100 Salil Mehta <salil.me...@huawei.com> wrote:
> CPUs Control device(\\_SB.PCI0) register interface for the x86 arch is based > on > PCI and is IO port based and hence existing CPUs AML code assumes _CRS objects > would evaluate to a system resource which describes IO Port address. But on > ARM > arch CPUs control device(\\_SB.PRES) register interface is memory-mapped hence > _CRS object should evaluate to system resource which describes memory-mapped > base address. Update build CPUs AML function to accept both IO/MEMORY region > spaces and accordingly update the _CRS object. > > Legacy CPU Hotplug uses Generic ACPI GPE Block Bit 2 (GPE.2) event handler to > notify OSPM about any CPU hot(un)plug events. GED framework uses new register > interface for cpu-(ctrl)dev. Make AML for GPE.2 event handler conditional. > > Co-developed-by: Keqian Zhu <zhukeqi...@huawei.com> > Signed-off-by: Keqian Zhu <zhukeqi...@huawei.com> > Signed-off-by: Salil Mehta <salil.me...@huawei.com> > Reviewed-by: Gavin Shan <gs...@redhat.com> > Tested-by: Vishnu Pajjuri <vis...@os.amperecomputing.com> Reviewed-by: Jonathan Cameron <jonathan.came...@huawei.com>
