We don't require c2 to be variable, so emphasize that.
We don't currently require c2 to be non-zero, but that will change.
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
---
target/sparc/translate.c | 40 ++++++++++++++++++++++------------------
1 file changed, 22 insertions(+), 18 deletions(-)
diff --git a/target/sparc/translate.c b/target/sparc/translate.c
index a8933d2fc3..32d29f16b5 100644
--- a/target/sparc/translate.c
+++ b/target/sparc/translate.c
@@ -183,7 +183,8 @@ typedef struct DisasContext {
typedef struct {
TCGCond cond;
- TCGv c1, c2;
+ TCGv c1;
+ int c2;
} DisasCompare;
// This function uses non-native bit order
@@ -974,15 +975,15 @@ static void gen_op_next_insn(void)
static void gen_compare(DisasCompare *cmp, bool xcc, unsigned int cond,
DisasContext *dc)
{
- TCGv t1, t2;
+ TCGv t1, t2, zero;
cmp->c1 = NULL;
- cmp->c2 = tcg_constant_tl(0);
+ cmp->c2 = 0;
switch (cond & 7) {
case 0x0: /* never */
cmp->cond = TCG_COND_NEVER;
- cmp->c1 = cmp->c2;
+ cmp->c1 = tcg_constant_tl(0);
break;
case 0x1: /* eq */
@@ -998,11 +999,12 @@ static void gen_compare(DisasCompare *cmp, bool xcc,
unsigned int cond,
case 0x2: /* le: Z | (N ^ V) */
cmp->cond = TCG_COND_LT;
cmp->c1 = t1 = tcg_temp_new();
+ zero = tcg_constant_tl(0);
if (TARGET_LONG_BITS == 32 || xcc) {
- tcg_gen_negsetcond_tl(TCG_COND_EQ, t1, cpu_cc_Z, cmp->c2);
+ tcg_gen_negsetcond_tl(TCG_COND_EQ, t1, cpu_cc_Z, zero);
} else {
tcg_gen_ext32u_tl(t1, cpu_icc_Z);
- tcg_gen_negsetcond_tl(TCG_COND_EQ, t1, t1, cmp->c2);
+ tcg_gen_negsetcond_tl(TCG_COND_EQ, t1, t1, zero);
}
t2 = tcg_temp_new();
tcg_gen_xor_tl(t2, cpu_cc_N, cpu_cc_V);
@@ -1079,7 +1081,7 @@ static void gen_fcompare(DisasCompare *cmp, unsigned int
cc, unsigned int cond)
/* For now we still generate a straight boolean result. */
cmp->cond = TCG_COND_NE;
cmp->c1 = r_dst = tcg_temp_new();
- cmp->c2 = tcg_constant_tl(0);
+ cmp->c2 = 0;
switch (cc) {
default:
@@ -1165,7 +1167,7 @@ static void gen_compare_reg(DisasCompare *cmp, int cond,
TCGv r_src)
{
cmp->cond = tcg_invert_cond(gen_tcg_cond_reg[cond]);
cmp->c1 = r_src;
- cmp->c2 = tcg_constant_tl(0);
+ cmp->c2 = 0;
}
static void gen_op_clear_ieee_excp_and_FTT(void)
@@ -2155,7 +2157,7 @@ static void gen_fmovs(DisasContext *dc, DisasCompare
*cmp, int rd, int rs)
or fold the comparison down to 32 bits and use movcond_i32. Choose
the later. */
c32 = tcg_temp_new_i32();
- tcg_gen_setcond_i64(cmp->cond, c64, cmp->c1, cmp->c2);
+ tcg_gen_setcondi_i64(cmp->cond, c64, cmp->c1, cmp->c2);
tcg_gen_extrl_i64_i32(c32, c64);
s1 = gen_load_fpr_F(dc, rs);
@@ -2175,7 +2177,7 @@ static void gen_fmovd(DisasContext *dc, DisasCompare
*cmp, int rd, int rs)
{
#ifdef TARGET_SPARC64
TCGv_i64 dst = gen_dest_fpr_D(dc, rd);
- tcg_gen_movcond_i64(cmp->cond, dst, cmp->c1, cmp->c2,
+ tcg_gen_movcond_i64(cmp->cond, dst, cmp->c1, tcg_constant_tl(cmp->c2),
gen_load_fpr_D(dc, rs),
gen_load_fpr_D(dc, rd));
gen_store_fpr_D(dc, rd, dst);
@@ -2189,10 +2191,11 @@ static void gen_fmovq(DisasContext *dc, DisasCompare
*cmp, int rd, int rs)
#ifdef TARGET_SPARC64
int qd = QFPREG(rd);
int qs = QFPREG(rs);
+ TCGv c2 = tcg_constant_tl(cmp->c2);
- tcg_gen_movcond_i64(cmp->cond, cpu_fpr[qd / 2], cmp->c1, cmp->c2,
+ tcg_gen_movcond_i64(cmp->cond, cpu_fpr[qd / 2], cmp->c1, c2,
cpu_fpr[qs / 2], cpu_fpr[qd / 2]);
- tcg_gen_movcond_i64(cmp->cond, cpu_fpr[qd / 2 + 1], cmp->c1, cmp->c2,
+ tcg_gen_movcond_i64(cmp->cond, cpu_fpr[qd / 2 + 1], cmp->c1, c2,
cpu_fpr[qs / 2 + 1], cpu_fpr[qd / 2 + 1]);
gen_update_fprs_dirty(dc, qd);
@@ -2323,7 +2326,7 @@ static bool advance_jump_cond(DisasContext *dc,
DisasCompare *cmp,
if (annul) {
TCGLabel *l1 = gen_new_label();
- tcg_gen_brcond_tl(tcg_invert_cond(cmp->cond), cmp->c1, cmp->c2, l1);
+ tcg_gen_brcondi_tl(tcg_invert_cond(cmp->cond), cmp->c1, cmp->c2, l1);
gen_goto_tb(dc, 0, npc, dest);
gen_set_label(l1);
gen_goto_tb(dc, 1, npc + 4, npc + 8);
@@ -2337,7 +2340,7 @@ static bool advance_jump_cond(DisasContext *dc,
DisasCompare *cmp,
tcg_gen_mov_tl(cpu_pc, cpu_npc);
tcg_gen_addi_tl(cpu_npc, cpu_npc, 4);
tcg_gen_movcond_tl(cmp->cond, cpu_npc,
- cmp->c1, cmp->c2,
+ cmp->c1, tcg_constant_tl(cmp->c2),
tcg_constant_tl(dest), cpu_npc);
dc->pc = npc;
break;
@@ -2352,9 +2355,9 @@ static bool advance_jump_cond(DisasContext *dc,
DisasCompare *cmp,
/* The condition for cpu_cond is always NE -- normalize. */
if (cmp->cond == TCG_COND_NE) {
- tcg_gen_sub_tl(cpu_cond, cmp->c1, cmp->c2);
+ tcg_gen_subi_tl(cpu_cond, cmp->c1, cmp->c2);
} else {
- tcg_gen_setcond_tl(cmp->cond, cpu_cond, cmp->c1, cmp->c2);
+ tcg_gen_setcondi_tl(cmp->cond, cpu_cond, cmp->c1, cmp->c2);
}
}
}
@@ -2554,7 +2557,7 @@ static bool trans_Tcc(DisasContext *dc, arg_Tcc *a)
flush_cond(dc);
lab = delay_exceptionv(dc, trap);
gen_compare(&cmp, a->cc, a->cond, dc);
- tcg_gen_brcond_tl(cmp.cond, cmp.c1, cmp.c2, lab);
+ tcg_gen_brcondi_tl(cmp.cond, cmp.c1, cmp.c2, lab);
return advance_pc(dc);
}
@@ -3913,8 +3916,9 @@ TRANS(SRA_i, ALL, do_shift_i, a, false, false)
static bool do_mov_cond(DisasContext *dc, DisasCompare *cmp, int rd, TCGv src2)
{
TCGv dst = gen_load_gpr(dc, rd);
+ TCGv c2 = tcg_constant_tl(cmp->c2);
- tcg_gen_movcond_tl(cmp->cond, dst, cmp->c1, cmp->c2, src2, dst);
+ tcg_gen_movcond_tl(cmp->cond, dst, cmp->c1, c2, src2, dst);
gen_store_gpr(dc, rd, dst);
return advance_pc(dc);
}
--
2.34.1
