Hi Peter, Yes, one of the strengths of the Xilinx CPLD's (and one of the reasons i love to work with them) is that they allow mixed bus voltages, at least for the particular device I have in mind:
The input buffer is compatible with standard 5V CMOS, 5V TTL and 3.3V signal levels. The input buffer uses the internal 5V voltage supply (VCCINT) to ensure that the input thresholds are constant and do not vary with the VCCIO voltage. The output driver is capable of supplying 24 mA output drive. All output drivers in the device may be configured for either 5 V TTL levels or 3.3 V levels by connecting the device output voltage supply (VCCIO) to a 5 V or 3.3 V voltage supply. We will obvioulsy not need mixed voltages in this case though. Cheers! /Mike > -----Original Message----- > From: [EMAIL PROTECTED] > [mailto:[EMAIL PROTECTED] On Behalf Of > [EMAIL PROTECTED] > Sent: Thursday, May 22, 2008 7:49 AM > To: [email protected] > Subject: Ql-Users Digest, Vol 51, Issue 10 > > Send Ql-Users mailing list submissions to > [email protected] > > To subscribe or unsubscribe via the World Wide Web, visit > http://lists.q-v-d.com/listinfo.cgi/ql-users-q-v-d.com > or, via email, send a message with subject or body 'help' to > [EMAIL PROTECTED] > > You can reach the person managing the list at > [EMAIL PROTECTED] > > When replying, please edit your Subject line so it is more > specific than "Re: Contents of Ql-Users digest..." > > > Today's Topics: > > 1. Re: New PCB for QubIDE ([EMAIL PROTECTED]) > > > ---------------------------------------------------------------------- > > Message: 1 > Date: Wed, 21 May 2008 12:06:42 +0200 > From: [EMAIL PROTECTED] > Subject: Re: [Ql-Users] New PCB for QubIDE > To: [EMAIL PROTECTED] > Message-ID: <[EMAIL PROTECTED]> > Content-Type: text/plain; charset=US-ASCII > > > I saw your schematics and was thinking that it might be possible to > > reduce the logic with a CPLD. I use Xilinx a lot in our > designs, and > > it really shrinks the board size and complexity. > > For the QL bus, did you consider the need for 5V tolerance? I > don't know about Xilinx in particular, but many 5V tolerant > CPLD and FPGA are moving toward obsolencense. It might be > better to use external 74-whatever level shifters in > combination with the lastest silicon, although it increases > board size somewhat. > > Maybe some chips have internal PCI clamp diodes, which can be > used to achieve 5V tolerance in combination with a series reistor. > > All the best, > Peter > > > > ------------------------------ > > _______________________________________________ > QL-Users mailing list > > > End of Ql-Users Digest, Vol 51, Issue 10 > **************************************** > _______________________________________________ QL-Users Mailing List http://www.q-v-d.demon.co.uk/smsqe.htm
