>
> Hello all,
>
> here's an awkward one I've come across in QLTDis for QL Toady - and I've
> figured it out for myself, but I don't like the solution !
>
> ADDQ = 0101 ddd0 ssxx xxxx
> SUBQ = 0101 ddd1 ssxx xxxx
> Scc = 0101 cccc 11xx xxxx
>
> Where 'ddd' = data and ranges from '000' to '111'
> 'ss' = size and can be '00', '01' or '10'
> 'cccc' = condition code and ranges from '0000' to '1111'
> 'xxxxxx' = effective address = don't care and can be anything !
>
> I have a mask for ADDQ/SUBQ of 1111 0001 0000 0000 which gives 0101 0000
> 0000 0000 for ADDQ and gives 0101 0001 0000 0000 for SUBQ. Unfortunately, it
> also gives 0100 0000 0000 0000 (ie ADDQ) for some Scc instructions and 0100
> 0001 0000 0000 (SUBQ) for others ! (ADDQ/SUBQ are tested before Scc so we
> hit a result for ADDQ/SUBQ before testing for an Scc).
>
> So here is the problem - how to set up my masks and results to get Scc
> and/or ADDQ/SUBQ regardless of the order they are tested ?
>
> Simple solution, move Scc above ADDQ/SUBQ in the testing order. Can this be
> guaranteed? I've gone cross eyed trying to figure out all the options etc.
> I have noticed that the size bits in ADDQ/SUBQ are never '11' and are always
> '11' for Scc so I could use this I suppose, but this effectively moves the
> ADDQ/SUBQ from type 18 to type 26 and is the same as moving the Scc test
> above ADDQ/SUBQ so I'm not fully convinced.
the ordering is quite essential when disassembling. The simple mask approach
only works with the perfect order - if at all. Generally order the tests for
the most specific instructions (all bits known or very few variable) first.
Bye
Richard
