Le mardi 26 mai 2020 03:59:59 UTC+2, johnbclements a écrit :
>
> > So far, I have made two attempts to work around these issues: (1) by 
> creating a metamodel-like data structure using Racket structs, and 
> transforming syntax objects into struct instances; or (2) using syntax 
> objects only and attaching context data to each of them as a syntax 
> property. 
> > Both have strengths and weaknesses, and I am still feeling that I am not 
> using Racket with the right mindset. 
>
> I think your (2) sounds like a lighter-weight solution. However, it 
> definitely does seem as though much of the difficulty here is related to 
> the differences between a more imperative and a more functional style.
>

I'm not sure that solution (2) is lighter. Maybe the weight is moved to 
another part of the implementation :)

I have set up an example at this address: 
https://gist.github.com/senshu/c6db95615b4b2567f168d6bfbe61655e

It is basically a very stripped-down hardware description language that 
borrows from VHDL and Verilog.
Like VHDL, the description of a circuit is split into an "entity" (the 
interface of the circuit) and an "architecture" (the implementation).
For the sake of simplicity, this example does not implement a complete 
model of computation.

The file "tiny-hdl-example-v1.rkt" implements a full adder and prints its 
truth table.
At this point, there is no name resolution, so I need to give redundant 
information in the "port-ref" expressions.
A better version of the language would allow to write:

(assign (h1 a) a)

instead of:

(assign (port-ref half-adder h1 a) (port-ref full-adder a))

because we know that

   - h1 is an instance of half-adder-arch, that has the entity half-adder,
   - the current architecture is full-adder-arch and its entity is 
   full-adder

I hope it clarifies my current concerns.

Guillaume

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