The entire queue seem to be visible in TX:70002840-7000287f and
RX:70002880-700028bf. I'm not sure where that might help yet if at all. All I
know is that I can write audio to any of the TX range and get sound out. Is it
possible DMA could run regardless of the bus lock? hrm...guess that's a big ??
A big boon would be to be able to flush cache ranges.
I'd still rather have 32-bit L-R pairs without shifting though. Gotta be a
solution to that shifty thing. :\
----- Original Message -----
From: Antonius Hellmann
To: Rockbox development
Sent: Saturday, May 19, 2007 4:14 AM
Subject: Sansa: avoid channel swapping issues
Based on an idea of jhMikeS I modified svn code (i2s-pp.c) in the following
way:
// IISFIFO_CFG |= 0x33; /* 12 slots full/empty config */
/* Bit2-3, Bit6-7 seem to have no meaning */
IISFIFO_CFG |= 0x22; /* 8 slots full/empty config */
which solves the channel swapping issues. The modification triggers the
interrupt already when 8 slots are empty, giving the system additional 45.3usec
to execute the fiq without the FIFO running empty. With current frequency
setting the cache releases the bus in time to execute the next fiq. The
drawback is, that 50% more fiq calls are issued. But the fiq handler itself has
some performance tuning potential.
