The reason for the need to shift is mismatched clock settings and these must be
right since e200 is the only pp target running the codec in slave mode. Heh!
Fixed...almost.
Now I need the correct settings for the following registers:
0x70002808 - i2s clock - change to something less than 0x3f :P
0x60006080 - codec clock - change to 0x00000007 (0x00000003 in OF)
I've got 'em close but the it's running a couple semitones sharp.
Perhaps this thing should be clocked as the OF does it? I tried that but
something's missing.
----- Original Message -----
From: Michael Sevakis
To: Rockbox development
Sent: Tuesday, May 22, 2007 2:59 AM
Subject: Re: Sansa: avoid channel swapping issues
Something noone has answered with "yes" or "no" yet:
To avoid channel swapping in all situations and leave the CPU load lighter,
should we not just lose the two least significant bits and simply use 32-bit
L-R pairs as is done in my patch? As soon as the reason for the two bit delay
is discovered, remove the shifting. That still leaves a dynamic range of ~80db
which is still larger than the new volume range and sounds just fine really.
I'm not at all for increasing the number of FIQs.
I'll emphasize again that PP502x (maybe 5002 as well) based iPods, since they
need no shift hack, will also be able to send data directly out of the PCM
buffer, lighten their FIQ load and become candidates for DMA audio transfer.
Those with iPods can take about 5min to verify that it also works for them.
Time to dump the excess of 32-bit samples imho since it is now known how to use
16-bit.
----- Original Message -----
From: Antonius Hellmann
To: Rockbox development
Sent: Saturday, May 19, 2007 4:14 AM
Subject: Sansa: avoid channel swapping issues
Based on an idea of jhMikeS I modified svn code (i2s-pp.c) in the following
way:
// IISFIFO_CFG |= 0x33; /* 12 slots full/empty config */
/* Bit2-3, Bit6-7 seem to have no meaning */
IISFIFO_CFG |= 0x22; /* 8 slots full/empty config */
which solves the channel swapping issues. The modification triggers the
interrupt already when 8 slots are empty, giving the system additional 45.3usec
to execute the fiq without the FIFO running empty. With current frequency
setting the cache releases the bus in time to execute the next fiq. The
drawback is, that 50% more fiq calls are issued. But the fiq handler itself has
some performance tuning potential.
