Does this change negatively affect the older sparc boards?
On Tue, Feb 11, 2014 at 11:25 AM, Sebastian Huber
<sebastian.hu...@embedded-brains.de> wrote:
> Recent LEON4 systems use a cache line size of 32 bytes.
> ---
> cpukit/score/cpu/sparc/rtems/score/cpu.h | 2 +-
> 1 files changed, 1 insertions(+), 1 deletions(-)
>
> diff --git a/cpukit/score/cpu/sparc/rtems/score/cpu.h
> b/cpukit/score/cpu/sparc/rtems/score/cpu.h
> index fe76fa5..17a9f54 100644
> --- a/cpukit/score/cpu/sparc/rtems/score/cpu.h
> +++ b/cpukit/score/cpu/sparc/rtems/score/cpu.h
> @@ -211,7 +211,7 @@ extern "C" {
> * The SPARC does not appear to have particularly strict alignment
> * requirements. This value was chosen to take advantages of caches.
> */
> -#define CPU_STRUCTURE_ALIGNMENT __attribute__ ((aligned (16)))
> +#define CPU_STRUCTURE_ALIGNMENT __attribute__ ((aligned (32)))
>
> #define CPU_TIMESTAMP_USE_INT64_INLINE TRUE
>
> --
> 1.7.7
>
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