On 2014-02-11 18:24, Gedare Bloom wrote:
Does this change negatively affect the older sparc boards?
This attribute is used only for two global structures. So the negative effect is a waste of 3 * 15 bytes in the worst case.
On Tue, Feb 11, 2014 at 11:25 AM, Sebastian Huber <[email protected]> wrote:Recent LEON4 systems use a cache line size of 32 bytes. --- cpukit/score/cpu/sparc/rtems/score/cpu.h | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/cpukit/score/cpu/sparc/rtems/score/cpu.h b/cpukit/score/cpu/sparc/rtems/score/cpu.h index fe76fa5..17a9f54 100644 --- a/cpukit/score/cpu/sparc/rtems/score/cpu.h +++ b/cpukit/score/cpu/sparc/rtems/score/cpu.h @@ -211,7 +211,7 @@ extern "C" { * The SPARC does not appear to have particularly strict alignment * requirements. This value was chosen to take advantages of caches. */ -#define CPU_STRUCTURE_ALIGNMENT __attribute__ ((aligned (16))) +#define CPU_STRUCTURE_ALIGNMENT __attribute__ ((aligned (32))) #define CPU_TIMESTAMP_USE_INT64_INLINE TRUE -- 1.7.7 _______________________________________________ rtems-devel mailing list [email protected] http://www.rtems.org/mailman/listinfo/rtems-devel
-- Sebastian Huber, embedded brains GmbH Address : Dornierstr. 4, D-82178 Puchheim, Germany Phone : +49 89 189 47 41-16 Fax : +49 89 189 47 41-09 E-Mail : [email protected] PGP : Public key available on request. Diese Nachricht ist keine geschäftliche Mitteilung im Sinne des EHUG. _______________________________________________ rtems-devel mailing list [email protected] http://www.rtems.org/mailman/listinfo/rtems-devel
