On 2014-04-22 16:16, Gedare Bloom wrote:
What is the need/use for this optimization?
The access to the thread dispatch disable level, the ISR nest level, the dispatch necessary, the executing and heir thread is faster since you don't have to calculate the address of the per-CPU control via the processor index.
With this optimization the context switch and interrupt support code are now identical for non-SMP and SMP configurations on SPARC. This alone is a good argument to use register g6 as the current per-CPU control pointer.
We work currently on a BSP for the XtratuM hypervisor on SPARC. On this hypervisor you have to use a system call to get the current processor index. This is very problematic in the interrupt prologue.
-- Sebastian Huber, embedded brains GmbH Address : Dornierstr. 4, D-82178 Puchheim, Germany Phone : +49 89 189 47 41-16 Fax : +49 89 189 47 41-09 E-Mail : sebastian.hu...@embedded-brains.de PGP : Public key available on request. Diese Nachricht ist keine geschäftliche Mitteilung im Sinne des EHUG. _______________________________________________ rtems-devel mailing list rtems-devel@rtems.org http://www.rtems.org/mailman/listinfo/rtems-devel
