On Tue, Nov 27, 2001 at 11:49:46AM -0500, Stefan Doehla wrote:
> Wasn't one of the goals of the whole APIC architecture reducing latencies???

No. Consider interrupt path in a SMP Intel IA32 board
        assert-> I/O Apic -arbitration -> serial interrupt buss
                                                |
                                                processor apic

You have a gain because you are not using the Pre-Cambrian era off chip
PIC on the standard UP Intel motherboard, but you have a loss because 
of the arbitration, serial bus, and 2 levels of interrupt controller.
So it's kind of a wash. 

We also believe that Linux performance is declining under the weight of
all the SMP "scaling" going on in 2.2+ and think this will be an issue
in 2.5 - but 2.5 is another headache.


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