On Wed, Nov 28, 2001 at 03:40:44PM -0500, Stefan Doehla wrote:
> Victor Yodaiken wrote:
> 
> >On Tue, Nov 27, 2001 at 11:49:46AM -0500, Stefan Doehla wrote:
> >
> >>Wasn't one of the goals of the whole APIC architecture reducing 
> >>latencies???
> >>
> >
> >No. Consider interrupt path in a SMP Intel IA32 board
> >     assert-> I/O Apic -arbitration -> serial interrupt buss
> >                                             |
> >                                             processor apic
> >
> >You have a gain because you are not using the Pre-Cambrian era off chip
> >PIC on the standard UP Intel motherboard, but you have a loss because 
> >of the arbitration, serial bus, and 2 levels of interrupt controller.
> >So it's kind of a wash.  
> 
> 
> This is the same I thought (but didn't know if it's true) as there are
> so many stages for the interrupts before they arrive at the right CPU.
> 
> If one reads Microsoft papers or Novell developer guidelines - only use 
> the APIC model ...
> 
> Anyway, the APIC thing runs with a higher clock and should be 
> programmable for smp affinity (I see there,s some code in RTL for this - 
> I just don't understand all the details ...).
> 
> Does RTL update the APIC register with the priorities of the tasks?

No. We don't care about hardware priorities.

> 
> Is it therefore possible to dedicate to one cpu only one interrupt when 
> there's a realtime thread running on this cpu?

Yes. 

> 
> Annotation: IRQ latency is 5-8 us with a non-SMP kernel.
> 
> 
> >We also believe that Linux performance is declining under the weight of
> >all the SMP "scaling" going on in 2.2+ and think this will be an issue
> >in 2.5 - but 2.5 is another headache.
> 
> so is 2.4.x with SMP not 'realtime'-compatible? My tests here show that a
> 
> 2.4.x kernel is not really realtime-stable. A 2.2.19 kernel is relative 
> okay, but 2.4.4 SMP is good for milliseconds, not microseconds ...

That seems wrong - maybe you have broken hardware.


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