Hi Jan,
it looks as actually only one statement is relevant, this is the addtional read
of the
status register directly after the write to it.
The following patch seems to be sufficient.
I do not understand why, but this seems to solve the issue...
--- rtnet-0.9.6/drivers/rt_eepro100.c.orig Fri Oct 20 12:35:44 2006
+++ rtnet-0.9.6/drivers/rt_eepro100.c Fri Oct 20 16:23:03 2006
@@ -1641,6 +1641,7 @@
/* Will change from 0xfc00 to 0xff00 when we start handling
FCP and ER interrupts --Dragan */
outw(status & 0xfc00, ioaddr + SCBStatus);
+ inw(ioaddr + SCBStatus); /* Required to avoid signal losses!! */
if (speedo_debug > 4)
rtdm_printk(KERN_DEBUG "%s: interrupt
status=%#4.4x.\n",
That's it for this week. Let's continue on monday!
Mathias
> > one changed part that I have identified in the ISR (e100intr()) of e100
> are the function calls to
> > e100_disable_clear_intr() and e100_set_intr_mask() that lead to additional
> accesses
> > to the NIC's (status, mask) registers.
> > And the patch was intended to do exactly the same accesses at eepro100.
>
> And that's not bad as we now have a working reference.
>
> >
> > Also, the e100intr processes only one interrupt at a time, i.e. it does
> not have the
> > do { } while(1); loop. This is the second part I modified.
>
> That depends on the model. Intel's stand-alone driver also still
> supports non-NAPI, i.e. the "classic" loop in the IRQ handler. The
> kernel now only knows NAPI: ack the IRQ and schedule some polling on the
> device in a bottom-half context (or task, can't tell right now).
>
--
Mathias Koehrer
[EMAIL PROTECTED]
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