M. Koehrer wrote: > Hi Jan, > > it looks as actually only one statement is relevant, this is the addtional > read of the > status register directly after the write to it. > The following patch seems to be sufficient. > I do not understand why, but this seems to solve the issue... > > --- rtnet-0.9.6/drivers/rt_eepro100.c.orig Fri Oct 20 12:35:44 2006 > +++ rtnet-0.9.6/drivers/rt_eepro100.c Fri Oct 20 16:23:03 2006 > @@ -1641,6 +1641,7 @@ > /* Will change from 0xfc00 to 0xff00 when we start handling > FCP and ER interrupts --Dragan */ > outw(status & 0xfc00, ioaddr + SCBStatus); > + inw(ioaddr + SCBStatus); /* Required to avoid signal losses!! > */ > > if (speedo_debug > 4) > rtdm_printk(KERN_DEBUG "%s: interrupt > status=%#4.4x.\n", >
Looks like this function from e100:
static inline void e100_write_flush(struct nic *nic)
{
/* Flush previous PCI writes through intermediate bridges
* by doing a benign read */
(void)readb(&nic->csr->scb.status);
}
Do you have your card on some nested PCI bus?
The e100 makes some use of this flush. I need to check if there are
other relevant spots in rt_eepro100.
Jan
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