Suraj N. Kurapati wrote: > I know the current Handle#posedge? and Handle#negedge? methods > aren't very precise (they check the current value when invoked) but > that can be fixed.
I have improved the value change / edge detection mechanism (do a `darcs pull` to get the patch). With this, I am now able to run a slightly simplified (in terms of clarity) version of your example (see the attached files) with GPL Cver. One thing to notice is that, in the spec file, there is a wait statement at the bottom of each "always" block. This ensures that we go to the next time step before attempting to detect an edge. Otherwise, the block will just loop forever because, for example, if clk0 has a posedge in the current time step, then clk0.posedge? will always return true while we remain in the current time step. Finally, the prototype also works. You will notice that, when the prototype is enabled, there is a 1 time step lag before we detect edges. This occurs because, for every time step, the prototype is run *strictly* in parallel with the specification, whereas the hardware is run *after* all threads in the specification have finished with the current time step.
//---------------------------
//
// Verilog Module
//
//---------------------------
module cadd_tb2;
reg clk0; initial clk0 = 'h0;
reg clk1; initial clk1 = 'h0;
initial forever #5 clk0 = ~clk0;
initial forever #7 clk1 = ~clk1;
// initial $dumpvars;
initial
begin
repeat(2000) @(posedge clk0);
$finish;
end
endmodule
cadd_tb2_spec.rb
Description: application/ruby
cadd_tb2_proto.rb
Description: application/ruby
$ rake -f cadd_tb2_runner.rake cver (in /home/sun/lab/ruby-vpi+calvin) cver +loadvpi=/home/sun/src/ruby-vpi/obj/cver.so:vlog_startup_routines_bootstrap cadd_tb2.v GPLCVER_2.11a of 07/05/05 (Linux-elf). Copyright (c) 1991-2005 Pragmatic C Software Corp. All Rights reserved. Licensed under the GNU General Public License (GPL). See the 'COPYING' file for details. NO WARRANTY provided. Today is Thu Aug 16 23:10:20 2007. Compiling source file "cadd_tb2.v" Highest level modules: cadd_tb2 monitoring handle: cadd_tb2.clk0 monitoring handle: cadd_tb2.clk1 Line 30 : clk0 = 1 (anyedge) : Simulation time is 5 Line 24 : clk0 = 1 (anyedge) : Simulation time is 5 Line 36 : clk1 = 1 (posedge) : Simulation time is 7 Line 30 : clk0 = 0 (anyedge) : Simulation time is 10 Line 24 : clk0 = 0 (anyedge) : Simulation time is 10 Line 48 : Simulation time is 11 Line 42 : clk1 = 0 (negedge) : Simulation time is 14 Line 30 : clk0 = 1 (anyedge) : Simulation time is 15 Line 24 : clk0 = 1 (anyedge) : Simulation time is 15 Line 30 : clk0 = 0 (anyedge) : Simulation time is 20 Line 24 : clk0 = 0 (anyedge) : Simulation time is 20 Line 36 : clk1 = 1 (posedge) : Simulation time is 21 Line 48 : Simulation time is 22 Line 30 : clk0 = 1 (anyedge) : Simulation time is 25 Line 24 : clk0 = 1 (anyedge) : Simulation time is 25 Line 42 : clk1 = 0 (negedge) : Simulation time is 28 Line 30 : clk0 = 0 (anyedge) : Simulation time is 30 Line 24 : clk0 = 0 (anyedge) : Simulation time is 30 Line 48 : Simulation time is 33 Line 36 : clk1 = 1 (posedge) : Simulation time is 35 Line 30 : clk0 = 1 (anyedge) : Simulation time is 35 Line 24 : clk0 = 1 (anyedge) : Simulation time is 35 Line 30 : clk0 = 0 (anyedge) : Simulation time is 40 Line 24 : clk0 = 0 (anyedge) : Simulation time is 40 Line 42 : clk1 = 0 (negedge) : Simulation time is 42 Line 48 : Simulation time is 44 Line 30 : clk0 = 1 (anyedge) : Simulation time is 45 Line 24 : clk0 = 1 (anyedge) : Simulation time is 45 Line 36 : clk1 = 1 (posedge) : Simulation time is 49 Line 30 : clk0 = 0 (anyedge) : Simulation time is 50 Line 24 : clk0 = 0 (anyedge) : Simulation time is 50 Line 48 : Simulation time is 55 Line 30 : clk0 = 1 (anyedge) : Simulation time is 55 Line 24 : clk0 = 1 (anyedge) : Simulation time is 55 Line 42 : clk1 = 0 (negedge) : Simulation time is 56 Line 30 : clk0 = 0 (anyedge) : Simulation time is 60 Line 24 : clk0 = 0 (anyedge) : Simulation time is 60 Line 36 : clk1 = 1 (posedge) : Simulation time is 63 Line 30 : clk0 = 1 (anyedge) : Simulation time is 65 Line 24 : clk0 = 1 (anyedge) : Simulation time is 65 Line 48 : Simulation time is 66 Line 42 : clk1 = 0 (negedge) : Simulation time is 70 Line 30 : clk0 = 0 (anyedge) : Simulation time is 70 Line 24 : clk0 = 0 (anyedge) : Simulation time is 70 Line 30 : clk0 = 1 (anyedge) : Simulation time is 75 Line 24 : clk0 = 1 (anyedge) : Simulation time is 75 Line 48 : Simulation time is 77 Line 36 : clk1 = 1 (posedge) : Simulation time is 77 Line 53 : Simulation time is 80 Halted at location **cadd_tb2.v(20) time 19995 from call to $finish. There were 7 error(s), 162 warning(s), and 0 inform(s).
