Suraj N. Kurapati wrote:
Calvin Wong wrote:
Also, this seg faults happens only for GPL Cver and NC-Verilog.
I get the segfault with GPL Cver but not with NC-Verilog (see the
attached ncsim.log file). I have NC-Verilog version 05.83-s003.
On vcs it works fine.
I ran it with VCS version Y-2006.06_Full64 and it didn't produce any
relevant output (see attached vcs.log file). Could you post the
output you see when you run the example in your environment?
Like I posted earlier, the fix that I have employed worked for both VCS
and GPL Cver.
I was able to gdb the nc-verilog and it appears to be aborting due to
some form
of licensing issue. I'll have to dig deeper into this. Here's the
newly revised
ruby test and the relevant output from GPL Cver, VCS, and ncsim.
# Adds support for Ruby version < 1.8
class Object
if (!(RUBY_VERSION =~ /^1\.8/))
def object_id
return id
end
end
end
# -- Required since no cleanup routines existed
# --
at_exit { Vpi::__extension__relay_verilog }
# --
# -- Barbones method to getting at?Edge working
# -- using sheer verilog vpi calls
# --
# -------------------------------------
#
# Scheduler Variables Declared Here!
#
# -------------------------------------
require 'monitor'
@@__scheduler__lock = Monitor.new # synchronizer
@@__scheduler__thread = {} # Individual threads
@@__scheduler__probe = nil # Arbitration thread
@@__scheduler__handler = {} # Might want to combine handler/cbRetData
@@__scheduler__cbRetData = {}
@@__scheduler__sigtype = {}
# -------------------------------------
#
# CW DEFINED FUNCTIONS HERE!
#
# -------------------------------------
def advanceTime waitTime
aVpiTime = Vpi::S_vpi_time.new
aVpiTime.type = Vpi::VpiSimTime
aVpiTime.high = 0
aVpiTime.low = waitTime
aVpiValue = Vpi::S_vpi_value.new
aVpiValue.format = Vpi::VpiSuppressVal
aCbData = Vpi::S_cb_data.new
aCbData.reason = Vpi::CbAfterDelay
aCbData.cb_rtn = Vpi::Vlog_relay_ruby
aCbData.obj = nil
aCbData.time = aVpiTime
aCbData.value = aVpiValue
aCbData.index = 0
aCbData.user_data = nil
@@__scheduler__lock.synchronize do
Vpi::vpi_free_object(Vpi::vpi_register_cb(aCbData))
Vpi::__extension__relay_verilog
end
end
def displaySimTime index
aVpiTime = Vpi::S_vpi_time.new
aVpiTime.type = Vpi::VpiSimTime
aVpiTime.high = 0
aVpiTime.low = 0
Vpi::vpi_get_time(nil, aVpiTime)
puts "Line #{index} : Simulation time is #{aVpiTime.low}"
end
def getCurrentValue aHandle, format=Vpi::VpiIntVal
aVpiValue = Vpi::S_vpi_value.new
aVpiValue.format = format
Vpi::vpi_get_value(aHandle, aVpiValue)
case format
when Vpi::VpiIntVal
return aVpiValue.value.integer
end
end
def atXEdge aHandle
@@__scheduler__lock.synchronize do
# 1. Register the callback
aVpiTime = Vpi::S_vpi_time.new
aVpiTime.type = Vpi::VpiSimTime
aVpiTime.high = 0
aVpiTime.low = 0
aVpiValue = Vpi::S_vpi_value.new
aVpiValue.format = Vpi::VpiIntVal
aCbData = Vpi::S_cb_data.new
aCbData.reason = Vpi::CbValueChange
aCbData.cb_rtn = Vpi::Vlog_relay_ruby
aCbData.obj = aHandle
aCbData.time = aVpiTime
aCbData.value = aVpiValue
aCbData.index = 0
aCbData.user_data = aHandle.object_id.to_s
if (@@__scheduler__cbRetData[aHandle.object_id.to_s] == nil)
@@__scheduler__cbRetData[aHandle.object_id.to_s] =
Vpi::vpi_register_cb(aCbData)
@@__scheduler__sigtype[aHandle.object_id.to_s] = "atXEdge"
end
# 2. Push thread onto the handler hash
if (@@__scheduler__handler[aHandle.object_id.to_s] == nil)
@@__scheduler__handler[aHandle.object_id.to_s] =
Array.new(1,Thread.current)
else
@@__scheduler__handler[aHandle.object_id.to_s] << Thread.current
end
end
Thread.stop
end
def atPosEdge aHandle
if (getCurrentValue(aHandle) == 0)
atXEdge(aHandle)
else
atXEdge(aHandle)
atXEdge(aHandle)
end
end
def atNegEdge aHandle
if (getCurrentValue(aHandle) == 0)
atXEdge(aHandle)
atXEdge(aHandle)
else
atXEdge(aHandle)
end
end
def waitSimTime waitTime
@@__scheduler__lock.synchronize do
aVpiTimeCurrentTime = Vpi::S_vpi_time.new
aVpiTimeCurrentTime.type = Vpi::VpiSimTime
Vpi::vpi_get_time(nil, aVpiTimeCurrentTime)
cbTime = aVpiTimeCurrentTime.low + waitTime # Absolute callback time
#1. Register the callback
aVpiTime = Vpi::S_vpi_time.new
aVpiTime.type = Vpi::VpiSimTime
aVpiTime.high = 0 # CW.TODO : assume time < 2^32
aVpiTime.low = waitTime
aVpiValue = Vpi::S_vpi_value.new
aVpiValue.format = Vpi::VpiSuppressVal
aCbData = Vpi::S_cb_data.new
aCbData.reason = Vpi::CbAfterDelay
aCbData.cb_rtn = Vpi::Vlog_relay_ruby
aCbData.obj = nil
aCbData.time = aVpiTime
aCbData.value = aVpiValue
aCbData.index = 0
aCbData.user_data = cbTime.object_id.to_s
if (@@__scheduler__cbRetData[cbTime.object_id.to_s] == nil)
@@__scheduler__cbRetData[cbTime.object_id.to_s] =
Vpi::vpi_register_cb(aCbData)
@@__scheduler__sigtype[cbTime.object_id.to_s] = "waitSimTime"
end
# 2. Push thread onto the handler hash
if (@@__scheduler__handler[cbTime.object_id.to_s] == nil)
@@__scheduler__handler[cbTime.object_id.to_s] =
Array.new(1,Thread.current)
else
@@__scheduler__handler[cbTime.object_id.to_s] << Thread.current
end
end
Thread.stop
end
# -------------------------------------
#
# TEST BEGINS HERE
#
# -------------------------------------
# Define the Probe Here
@@__scheduler__probe = Thread.new do
loop do
unless (@@__scheduler__thread.empty?)
all_threads_asleep = true
@@__scheduler__thread.each do |key,value|
all_threads_asleep &= value.stop?
end
Thread.pass # --[CW.TODO] : This hack seems to work
if ((all_threads_asleep) && (!@@__scheduler__handler.empty?))
@@__scheduler__lock.synchronize do
Vpi::__extension__relay_verilog
reason = Vpi::__extension__relay_ruby_reason
@@__scheduler__handler[reason.user_data].each { |aThread|
aThread.wakeup }
@@__scheduler__handler.delete(reason.user_data)
# -- Only signal of type atXEdge needs to have the callback
# -- routine removed from the simulator
if (@@__scheduler__sigtype[reason.user_data] == "atXEdge")
Vpi::vpi_remove_cb(@@__scheduler__cbRetData[reason.user_data])
end
@@__scheduler__cbRetData.delete(reason.user_data)
@@__scheduler__sigtype.delete(reason.user_data)
end
end
end
Thread.pass
end
end
# Advance 1 time unit for now
advanceTime 1
clk0 = Vpi::vpi_handle_by_name("cadd_tb.clk0", nil)
clk1 = Vpi::vpi_handle_by_name("cadd_tb.clk1", nil)
@@__scheduler__thread['t0'] = Thread.new do
5.times do
atXEdge(clk0)
displaySimTime "#{__LINE__} : T0.clk0 = #{getCurrentValue(clk0)}"
end
end
@@__scheduler__thread['t1'] = Thread.new do
5.times do
atXEdge(clk0)
displaySimTime "#{__LINE__} : T1.clk0 = #{getCurrentValue(clk0)}"
end
end
@@__scheduler__thread['t2'] = Thread.new do
5.times do
atPosEdge(clk1)
displaySimTime "#{__LINE__} : T2.clk1 = #{getCurrentValue(clk1)}"
end
end
@@__scheduler__thread['t3'] = Thread.new do
5.times do
atNegEdge(clk1)
displaySimTime "#{__LINE__} : T3.clk1 = #{getCurrentValue(clk1)}"
end
end
@@__scheduler__thread['t4'] = Thread.new do
5.times do
waitSimTime 11
displaySimTime "#{__LINE__}"
end
end
@@__scheduler__thread['t0'].join
@@__scheduler__thread['t1'].join
@@__scheduler__thread['t2'].join
@@__scheduler__thread['t3'].join
@@__scheduler__thread['t4'].join
@@__scheduler__thread.delete('t0')
@@__scheduler__thread.delete('t1')
@@__scheduler__thread.delete('t2')
@@__scheduler__thread.delete('t3')
@@__scheduler__thread.delete('t4')
advanceTime 10
displaySimTime __LINE__
puts "scheduler.thread.size = #{@@__scheduler__thread.size}"
puts "scheduler.handler.size = #{@@__scheduler__handler.size}"
puts "scheduler.cbRetData.size = #{@@__scheduler__cbRetData.size}"
puts "scheduler.sigtype.size = #{@@__scheduler__sigtype.size}"
RUBYVPI_BOOT_LOADER = ./cadd_thread.rb
RUBYVPI_BOOT_TARGET = cadd_tb
Using cver
cmd = './bin/cver +loadvpi=./obj/cver.so:vlog_startup_routines_bootstrap
+incdir+. ./cadd.v ./cadd_tb.v '
GPLCVER_2.12a of 05/16/07 (Linux-elf).
Copyright (c) 1991-2007 Pragmatic C Software Corp.
All Rights reserved. Licensed under the GNU General Public License (GPL).
See the 'COPYING' file for details. NO WARRANTY provided.
Today is Thu Aug 16 21:52:15 2007.
Invoking vlog_startup_routines_bootstrap()
Compiling source file "./cadd.v"
Compiling source file "./cadd_tb.v"
Highest level modules:
cadd_tb
Line 247 : T1.clk0 = 1 : Simulation time is 5
Line 240 : T0.clk0 = 1 : Simulation time is 5
Line 254 : T2.clk1 = 1 : Simulation time is 7
Line 247 : T1.clk0 = 0 : Simulation time is 10
Line 240 : T0.clk0 = 0 : Simulation time is 10
Line 261 : T3.clk1 = 0 : Simulation time is 14
Line 247 : T1.clk0 = 1 : Simulation time is 15
Line 240 : T0.clk0 = 1 : Simulation time is 15
Line 268 : Simulation time is 16
Line 247 : T1.clk0 = 0 : Simulation time is 20
Line 240 : T0.clk0 = 0 : Simulation time is 20
Line 254 : T2.clk1 = 1 : Simulation time is 21
Line 247 : T1.clk0 = 1 : Simulation time is 25
Line 240 : T0.clk0 = 1 : Simulation time is 25
Line 268 : Simulation time is 27
Line 261 : T3.clk1 = 0 : Simulation time is 28
Line 254 : T2.clk1 = 1 : Simulation time is 35
Line 268 : Simulation time is 38
Line 261 : T3.clk1 = 0 : Simulation time is 42
Line 268 : Simulation time is 49
Line 254 : T2.clk1 = 1 : Simulation time is 49
Line 261 : T3.clk1 = 0 : Simulation time is 56
Line 268 : Simulation time is 60
Line 254 : T2.clk1 = 1 : Simulation time is 63
Line 261 : T3.clk1 = 0 : Simulation time is 70
Line 284 : Simulation time is 80
scheduler.thread.size = 0
scheduler.handler.size = 0
scheduler.cbRetData.size = 0
scheduler.sigtype.size = 0
Halted at location **./cadd_tb.v(32) time 19995 from call to $finish.
There were 0 error(s), 3 warning(s), and 6 inform(s).
RUBYVPI_BOOT_LOADER = ./cadd_thread.rb
RUBYVPI_BOOT_TARGET = cadd_tb
Using vcs
cmd = '/auto/edatools/synopsys/vcs/v7.2R7/linux/bin/vcs -R +v2k +vpi +cli
+acc+3 +vcs+lic+wait -P ./lib/pli.tab -load
./obj/vcs.so:vlog_startup_routines_bootstrap +incdir+. ./cadd.v ./cadd_tb.v '
Chronologic VCS (TM)
Version 7.2R7 -- Thu Aug 16 21:52:58 2007
Copyright (c) 1991-2004 by Synopsys Inc.
ALL RIGHTS RESERVED
This program is proprietary and confidential information of Synopsys Inc.
and may be used and disclosed only as authorized in a license agreement
controlling such use and disclosure.
Invoking vlog_startup_routines_bootstrap()
***** Warning: ACC/CLI capabilities have been enabled for the entire design.
For faster performance enable module specific capability in pli.tab file
Parsing design file './cadd.v'
Parsing design file './cadd_tb.v'
Top Level Modules:
cadd_tb
TimeScale is 1 ns / 1 ns
Starting vcs inline pass...
1 module and 0 UDP read.
recompiling module cadd_tb
if [ -x ../simv ]; then chmod -x ../simv; fi
gcc -o ../simv 5NrI_d.o 5NrIB_d.o 30qp_1_d.o SIM_l.o
/auto/edatools/synopsys/vcs/v7.2R7/gui/virsim/linux/vcdplus/vcs7_2/libvirsim.a
/auto/edatools/synopsys/vcs/v7.2R7/linux/lib/libvcsnew.so
/auto/edatools/synopsys/vcs/v7.2R7/linux/lib/ctype-stubs_32.a -ldl -lm -lc
-ldl
../simv up to date
Chronologic VCS simulator copyright 1991-2004
Contains Synopsys proprietary information.
Compiler version 7.2R7; Runtime version 7.2R7; Aug 16 21:52 2007
Invoking vlog_startup_routines_bootstrap()
Line 247 : T1.clk0 = 1 : Simulation time is 5
Line 240 : T0.clk0 = 1 : Simulation time is 5
Line 254 : T2.clk1 = 1 : Simulation time is 7
Line 247 : T1.clk0 = 0 : Simulation time is 10
Line 240 : T0.clk0 = 0 : Simulation time is 10
Line 261 : T3.clk1 = 0 : Simulation time is 14
Line 247 : T1.clk0 = 1 : Simulation time is 15
Line 240 : T0.clk0 = 1 : Simulation time is 15
Line 268 : Simulation time is 16
Line 247 : T1.clk0 = 0 : Simulation time is 20
Line 240 : T0.clk0 = 0 : Simulation time is 20
Line 254 : T2.clk1 = 1 : Simulation time is 21
Line 247 : T1.clk0 = 1 : Simulation time is 25
Line 240 : T0.clk0 = 1 : Simulation time is 25
Line 268 : Simulation time is 27
Line 261 : T3.clk1 = 0 : Simulation time is 28
Line 254 : T2.clk1 = 1 : Simulation time is 35
Line 268 : Simulation time is 38
Line 261 : T3.clk1 = 0 : Simulation time is 42
Line 268 : Simulation time is 49
Line 254 : T2.clk1 = 1 : Simulation time is 49
Line 261 : T3.clk1 = 0 : Simulation time is 56
Line 268 : Simulation time is 60
Line 254 : T2.clk1 = 1 : Simulation time is 63
Line 261 : T3.clk1 = 0 : Simulation time is 70
Line 284 : Simulation time is 80
scheduler.thread.size = 0
scheduler.handler.size = 0
scheduler.cbRetData.size = 0
scheduler.sigtype.size = 0
$finish at simulation time 19995
V C S S i m u l a t i o n R e p o r t
Time: 19995 ns
CPU Time: 0.020 seconds; Data structure size: 0.0Mb
Thu Aug 16 21:53:00 2007
CPU time: .070 seconds to compile + .080 seconds to link + .090 seconds in
simulation
RUBYVPI_BOOT_LOADER = ./cadd_thread.rb
RUBYVPI_BOOT_TARGET = cadd_tb
Using ncsim
cmd = '/nfs/edatools/cadence/ius/v5.7/Linux/tools/inca/bin/ncverilog --X
+access+rwc +plinowarn +loadvpi=./obj/ncsim:vlog_startup_routines_bootstrap
+incdir+. ./cadd.v ./cadd_tb.v '
ncverilog: 05.70-p001: (c) Copyright 1995-2006 Cadence Design Systems, Inc.
Invoking vlog_startup_routines_bootstrap()
Caching library 'worklib' ....... Caching library
'worklib' ....... Done
Done
Elaborating the design hierarchy:
Elaborating the design hierarchy:
Building instance overlay tables: Building instance overlay
tables: ........................................ Done
Done
Loading native compiled code: Loading native compiled code:
........................................ Done
Done
Building instance specific data structures.
Design hierarchy summary:
Instances Unique
Modules: 2 2
Registers: 6 6
Scalar wires: 2 -
Vectored wires: 3 -
Always blocks: 1 1
Initial blocks: 9 9
Pseudo assignments: 4 4
Simulation timescale: 1ns
Writing initial simulation snapshot: Building instance specific data
structures.
Design hierarchy summary:
Instances Unique
Modules: 2 2
Registers: 6 6
Scalar wires: 2 -
Vectored wires: 3 -
Always blocks: 1 1
Initial blocks: 9 9
Pseudo assignments: 4 4
Simulation timescale: 1ns
Writing initial simulation snapshot: worklib.cadd_tb:v
worklib.cadd_tb:v
Loading snapshot Loading snapshot worklib.cadd_tb:vworklib.cadd_tb:v
........................................ Done
Done
Invoking vlog_startup_routines_bootstrap()
ncsim> ncsim> source
/auto/edatools/cadence/ldv/current/Linux/tools/inca/files/ncsimrc
source /auto/edatools/cadence/ldv/current/Linux/tools/inca/files/ncsimrc
ncsim> ncsim> run
run
ncsimncsim: : *internal* (*internal* (Unexpected signal #6, program terminated
(null)Unexpected signal #6, program terminated (null)).
).
Observed simulation time : 0 FS + 0
Please contact Cadence Design Systems about this problem
Observed simulation time : 0 FS + 0
Please contact Cadence Design Systems about this problem
and provide enough information to help us reproduce it.
and provide enough information to help us reproduce it.
TOOL: ncverilog 05.70-p001: Exiting on Aug 16, 2007 at 21:54:40 PDT
(total: 00:00:10)
