Edwin Blink wrote: > IN A,(n) 12 Ts (all ports)
The original tests I did for SimCoup� showed ports &F8 to &FF always required ASIC attention, giving an extra 4 tstate penalty if not correctly aligned (even in the border area). Just in case your test avoided it, could you try it with a NOP before the IN instruction? (I don't have access to my real SAM at the moment). For that I'd expect to see 16 tstates (including the NOP) for ports < &F8 and 20 tstates for >= &F8. Removing the IN A,(n) port delay in SimCoup� breaks a few of timing-sensitive demos, so I'm fairly sure it should be there. I'm not aware of any other timing issues, so I think everything is covered! Dave Laundon's timing enhancements rely on building the timing step by step, so inter-instruction delays are taken into account. For the breakdown list used see: http://www.geocities.com/SiliconValley/Peaks/3938/z80ins.txt The other I/O instructions are affected in the same way, depending on which port is accessed, where in the instruction the I/O occurs relative to the current display cycle position. Of course, that's still ignoring possible memory contention, including mode 1 contention, and the unrounded timings if the code is running in the ROM or external memory. Building a definitive instruction timing list is difficult because it depends on so much! :-) Si
