> 
> Well, my holy quest for the Z800 has almost drawn to a close.
> As you may (or more than likely, may not) be aware, I have for many 
> years now planned to customise the SAM by the replacement of the 
> weakest part of the system... the CPU.. :)
> 
> [ nb 'A Z8108 internally clocked at 24Mhz linked to a 6Mhz bus']
> 
> After a strenous search of our universities' VAST library (how DO you 
> indicate a sarcastic tone of voice on an email message?... oh, never 
> mind..) I have finally found.. the 1983/84 Zilog Data book, with full 
> specs on the Z800 series. wow. I can see you're all impressed 
> already.
> 
> It would appear that my earlier theory that its just a straight cut 
> and paste job, so to speak, was ever so slightly misguided. As I 
> suspected, the Z8108 is indeed fully pin compatible with the Z80 
> (weeeelll... after you rearrange and demultiplex them, anyway.. )...
> execept for one teeny problem.
> 
> Now, if you would all care to turn to your diagrams of the Z80... 
> (pause for the rustle of papers), you will see it has a  CLK input. 
> No surprise there. In fact, the surprise would come if... oh, never 
> mind... I'll get on with it.... To cut a long story short, as we are 
> all well aware the ASIC dishes out the Z80's clock signal on the SAM,
> and thus the ASIC basically drives the bus (not in the literal sense 
> of the word, but it requires exact timing, hence it gives the CPU 
> clock). Now, if I were to place a Z800, which has a clock 
> output, and a direct crystal/oscillator input, into this system, 
> things get messy... especially since the Z800 requires double the 
> clock input frequency that the bus is meant to run at. So all I need now 
> is an accurate clock doubler that feeds from the ASIC into the two 
> crystal inputs of the Z800, and reference it against its own clock output 
> somehow so it gives its clock signals at exactly the same time the 
> ASIC would dish out the clock signals to the Z80......   
> heeellllpppp!
> 
>


Could you get the clock using a phase-locked loop (PLL)?
Set the PLL to 12MHz, divide the output by two and compare the
divide signal with the ASIC's 6MHz output.

Actually, I don't even know if you need to worry about tying
the Z800 (can you actually still buy them?) clock to the SAM
clock - the ASIC is going to insert wait states anyway, and
its going to tie those wait to its own 6MHz clock.

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