> > Could you get the clock using a phase-locked loop (PLL)? > Set the PLL to 12MHz, divide the output by two and compare the > divide signal with the ASIC's 6MHz output.
Nawww.. just stick an edge-triggered bistable into the circuit -- two in series will create a neat little 24MHz output (I think...) > Actually, I don't even know if you need to worry about tying > the Z800 (can you actually still buy them?) clock to the SAM > clock - the ASIC is going to insert wait states anyway, and > its going to tie those wait to its own 6MHz clock. Well, Colin PIggot tried it with an 8MHz Z80C and the ASIC /did not/ want to know. The bus, it seems, has to be at 6MHz... Simon Cooke
