On (17 Feb 95) [EMAIL PROTECTED] wrote to All... s> From: Simon Cooke <[EMAIL PROTECTED]> s> Date: Fri, 17 Feb 1995 10:24:28 +0000 (GMT)
s> I think that the clocks aren't restored until the RESET line has gone s> high again!!! At least, that's as much as I can figure out from the fact s> that if you reset the sound chip --on reset-- as soon as the processor s> gets around to it, then the chip nine times out of ten ignores it and s> doesn't stop making that awful sound... How about a NE555 set in MonoStable mode and it's output fed to a 1 transistor inverter and fed to the ASIC ONLY and set the low-pulse width to just enough to reliably reset the ASIC but substantially shorter than the main /RESET line that goes to the z80-CPU, FDC and UART chips. That way the support chips will get their clocks etc before /RESET goes inactive:-) That could fix ALL FDC chips, internal or external unlike the patch chip that just fixes the internal drives;-) s> Yeah, I was thinking of doing that test... we've now found the cause of a s> few bugs in the MultiROM and the HD interface though :) I saw you mention somthing about decoding M1 in another post.... I suspect you/martin were using /IORQ with address decoding which IM2 interupts in conjuction with a floating address bus would trigger false I/O decodes? Normaly you should use /RD and or /WR to qualify the potentialy decoded address, AFAIK that's how the ASIC does it as do most other devices:-) Though using M1 I suppose you can get a decoded I/O address using less gates though:-) Johnathan. ... In theory, theory and practice are the same. In practice, they're not. -- |Fidonet: Johnathan Taylor 2:2501/307.9 |Internet: [EMAIL PROTECTED] | | Standard disclaimer: The views of this user are strictly his own.
