> On (14 Feb 95) [EMAIL PROTECTED] wrote... > BTW that ASIC reset 8MHz clock loss bug also affects the 6MHz CPU clock and > causes some bits to lose their memory during a hard-reset. I think many > inconsistancies in the SAM could be fixed by simply stealing some of the 24MHz > master clock and hard dividing it externaly and usin that to replace the > 6/8MHz clock signals. Also could use a 12MHz output for when I can get hold > of that Z84C50 CPU;-) *grins*
I think that the clocks aren't restored until the RESET line has gone high again!!! At least, that's as much as I can figure out from the fact that if you reset the sound chip --on reset-- as soon as the processor gets around to it, then the chip nine times out of ten ignores it and doesn't stop making that awful sound... > s> Yeah, but could it be the IORQ & M1 both going low at the start of the > s> interrupt that causes the problems? Could the ASIC be receiving spurious > s> IO read/writes? > > It shouldn't as that's the standard z80/8080 interupt acknowledge cycle, in > ALL modes, Bruce MUST've known that for years before the ASIC was designed and > as the ASIC is the only current source for interupts to the z80 it shouldn't > be looking for any I/O whilst it's interupting the z80... Anyway I'd expect > that IORQ would have to be qualified by a corisponding RD or WR signal prior > to initiating ASIC port decoding... Though only Bruce would have such insider > details:-( > > You could test the theory by using an active M1 to disqualify the active IORQ > to the ASIC. I don't think it'd make any difference. Yeah, I was thinking of doing that test... we've now found the cause of a few bugs in the MultiROM and the HD interface though :) > Oh thanks for explaining to imc about zilog peripherals and RETI, saves my > typin:-) No problemo > Regards > Johnathan. Simon
