> Actually, I'm kind of worried about the UltraRisc chip he's come up with > -- after all, how RISC is RISC? I mean, subtract and branch on result is > as RISC as you can get, (well, add a store command to move data to/from > memory and you're set). >
RISC isn't about having as few instructions as possible - it's about having no more than will give optimum performance. Adding instructions usually slows down the processor, so it's a case of weighing up the increase in performance given by that particular instruction, against the overall reduction in speed caused to all the other instructions by the addition of that new instruction. In fact, I'd stick my neck out and say that if it has a nice regular instruction format, and it can be decoded quickly, and it easily pipelines, then you can add it to the instruction set. Andy
