Hi,
We have the following needs for *System Validation Engineer Needed *in TX. Please find if you are comfortable with the given Job description and send me your Updated Resume along with your expected rate for this project ASAP System Validation Engineer Needed Location: Austin, TX *Duration: 6 months* *1 position for Design & Validation Engineer:* Exhaustive hands-on experience in Verilog / System Verilog, Shell Scripting. Experience on Altera Q-II flow, Cadence Build Gates / PKS Synthesis tool and Linux environment is highly desirable. Design experience in PCIe, HDMI, HD-SDI, Image Processing Pipeline, DDR3C, H.264, XAUI, J2K Decoder etc. logic block is preferable. Regards...!! *Prabhu Vedhanayagam* Phone: 925-353-3769 | [email protected] Web Site: www.tridentconsultinginc.com LinkedIn URL: http://www.linkedin.com/in/prabhu020884 (Note: We respect your Online Privacy. This is not an unsolicitedmail. This mail cannot be considered Spam as long as we include Contact information and a method to be removed from our mailing list. If you are not interested in receiving our e-mails then please reply with a "REMOVE" in the subject line. Sorry for any inconvenience caused.) -- *************************************************************************************** For all SAP related tutorials,Articles,Faqs,Tips www.sapbrainsonline.com **************************************************************************************** You received this message because you are subscribed to the Google Groups "sapbrains" group. To post to this group, send email to [email protected] To unsubscribe from this group, send email to [email protected] For more options, visit this group at http://groups.google.com/group/sapbrains?hl=en
