Yes, I am aware that the STM8 has a pipelined architecture. I don't
think that this can be wholly explained by that.
Let me provide some context. My benchmark for my strcpsn implementation
performs 1000 iterations of the following:
strcspn("1620376B3653",
"abcdefghijklmnopqrstuvwxyzABCDEFGHIJKLMNOPQRSTUVWXYZ");
I record the total number of cycles taken using a ucSim timer. The timer
is triggered by a write to a GPIO port, which I do in the benchmark code
immediately prior to and after the iteration loop. When running on real
hardware, the same GPIO port write is setting/clearing a pin, which is
hooked to a logic analyser and the execution time measured in the
capture trace.
When plotted on a chart alongside all other of my assembly routines,
such that the Y axis scales are proportional (i.e. largest cycle count
aligns with largest execution time), the strcspn benchmark is the only
one with a significant discrepancy between ucSim and H/W.
The cycle count from ucSim is 2,854,010. The H/W execution time is (from
an average of 3 runs) 257.267 ms. The sim cycle count is only 84% of the
H/W execution time. This means that if the sim result were to correlate
with the H/W timing, it would need to take approx. 544,000 cycles more!
Something is not right, and I think it is with ucSim.
I have attached an image of the chart. Hopefully it will make it to the
list.
Regards,
Basil
On 22/07/2020 18:09, Eric Rullens wrote:
Hi Basil,
Maybe it is not that simple. The STM8 has a prefetch buffer (for flash
access) and also sports pipelined execution. Under certain conditions the
pipeline is flushed and the CPU may be stalled. Then execution time is not
simply the sum of the (nominal) number cycles to execute an instruction. The
programming manual (PM0044) has more information on this.
Maybe due to the used addressing modes and looping strcspn() this is
particularly sensitive to these effects? If so, carefully arranging and/or
aligning instructions might help.
Eric
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