Hi Basil,

Maybe it is not that simple. The STM8 has a prefetch buffer (for flash
access) and also sports pipelined execution. Under certain conditions the
pipeline is flushed and the CPU may be stalled. Then execution time is not
simply the sum of the (nominal) number cycles to execute an instruction. The
programming manual (PM0044) has more information on this.

Maybe due to the used addressing modes and looping strcspn() this is
particularly sensitive to these effects? If so, carefully arranging and/or
aligning instructions might help.

 Eric


> -----Original Message-----
> From: Basil Hussain [mailto:ba...@stasisleak.uk] 
> Sent: woensdag 22 juli 2020 15:11
> To: SDCC User Mailing List
> Subject: [Sdcc-user] ucSim instruction cycle counts - where defined?
> 
> Hi all,
> 
> In ucSim, where or what defines how many simulated cycles 
> each instruction takes? Specifically, I am looking at the 
> STM8 simulator.
> 
> I recently got around to running the benchmark of my assembly 
> implementations of some string.h functions (see patch #333 
> for details) on physical hardware and was surprised to find a 
> significant discrepancy for one piece of code in the 
> relationship between cycles measured by ucSim and execution 
> time on real hardware.
> 
> When plotted on an equivalent scale, sim cycles vs. H/W exec 
> time corresponds very closely everywhere, except for my 
> strcspn routine, where ucSim cycle count is significantly 
> lower compared to the H/W execution time.
> 
> I have a feeling ucSim might not be using the correct number 
> of cycles somewhere. Not sure where, though, because I'm not 
> using any unusual instructions in the strcspn assembly code 
> that aren't used elsewhere.
> 
> Regards,
> Basil Hussain
> 
> 
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