[edk2-devel] [PATCH 09/15] [platforms/devel-riscv]: U500Pkg/Library: Initial version of PlatformBootManagerLib
SiFive RISC-V U500 Platform Boot Manager library.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Gilbert Chen
---
.../Library/PlatformBootManagerLib/MemoryTest.c| 1110
.../PlatformBootManagerLib/PlatformBootManager.c | 269 +
.../PlatformBootManagerLib/PlatformBootManager.h | 141 +++
.../PlatformBootManagerLib.inf | 72 ++
.../Library/PlatformBootManagerLib/PlatformData.c | 54 +
.../Library/PlatformBootManagerLib/Strings.uni | Bin 0 -> 3922 bytes
6 files changed, 1646 insertions(+)
create mode 100644
Platform/RiscV/SiFive/U500Pkg/Library/PlatformBootManagerLib/MemoryTest.c
create mode 100644
Platform/RiscV/SiFive/U500Pkg/Library/PlatformBootManagerLib/PlatformBootManager.c
create mode 100644
Platform/RiscV/SiFive/U500Pkg/Library/PlatformBootManagerLib/PlatformBootManager.h
create mode 100644
Platform/RiscV/SiFive/U500Pkg/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf
create mode 100644
Platform/RiscV/SiFive/U500Pkg/Library/PlatformBootManagerLib/PlatformData.c
create mode 100644
Platform/RiscV/SiFive/U500Pkg/Library/PlatformBootManagerLib/Strings.uni
diff --git
a/Platform/RiscV/SiFive/U500Pkg/Library/PlatformBootManagerLib/MemoryTest.c
b/Platform/RiscV/SiFive/U500Pkg/Library/PlatformBootManagerLib/MemoryTest.c
new file mode 100644
index 000..841e3d9
--- /dev/null
+++ b/Platform/RiscV/SiFive/U500Pkg/Library/PlatformBootManagerLib/MemoryTest.c
@@ -0,0 +1,1110 @@
+/** @file
+ Perform the RISC-V platform memory test
+
+Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights
reserved.
+Copyright (c) 2004 - 2015, Intel Corporation. All rights reserved.
+
+This program and the accompanying materials
+are licensed and made available under the terms and conditions of the BSD
License
+which accompanies this distribution. The full text of the license may be
found at
+http://opensource.org/licenses/bsd-license.php
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include "PlatformBootManager.h"
+
+EFI_HII_HANDLE gStringPackHandle = NULL;
+EFI_GUID mPlatformBootManagerStringPackGuid = {
+ 0x154dd51, 0x9079, 0x4a10, { 0x89, 0x5c, 0x9c, 0x7, 0x72, 0x81, 0x57, 0x88 }
+ };
+// extern UINT8 BdsDxeStrings[];
+
+//
+// BDS Platform Functions
+//
+/**
+
+ Show progress bar with title above it. It only works in Graphics mode.
+
+ @param TitleForeground Foreground color for Title.
+ @param TitleBackground Background color for Title.
+ @param Title Title above progress bar.
+ @param ProgressColor Progress bar color.
+ @param ProgressProgress (0-100)
+ @param PreviousValue The previous value of the progress.
+
+ @retval EFI_STATUS Success update the progress bar
+
+**/
+EFI_STATUS
+PlatformBootManagerShowProgress (
+ IN EFI_GRAPHICS_OUTPUT_BLT_PIXEL TitleForeground,
+ IN EFI_GRAPHICS_OUTPUT_BLT_PIXEL TitleBackground,
+ IN CHAR16*Title,
+ IN EFI_GRAPHICS_OUTPUT_BLT_PIXEL ProgressColor,
+ IN UINTN Progress,
+ IN UINTN PreviousValue
+ )
+{
+ EFI_STATUS Status;
+ EFI_GRAPHICS_OUTPUT_PROTOCOL *GraphicsOutput;
+ EFI_UGA_DRAW_PROTOCOL *UgaDraw;
+ UINT32 SizeOfX;
+ UINT32 SizeOfY;
+ UINT32 ColorDepth;
+ UINT32 RefreshRate;
+ EFI_GRAPHICS_OUTPUT_BLT_PIXEL Color;
+ UINTN BlockHeight;
+ UINTN BlockWidth;
+ UINTN BlockNum;
+ UINTN PosX;
+ UINTN PosY;
+ UINTN Index;
+
+ if (Progress > 100) {
+return EFI_INVALID_PARAMETER;
+ }
+
+ UgaDraw = NULL;
+ Status = gBS->HandleProtocol (
+ gST->ConsoleOutHandle,
+ ,
+ (VOID **)
+ );
+ if (EFI_ERROR (Status) && FeaturePcdGet (PcdUgaConsumeSupport)) {
+GraphicsOutput = NULL;
+
+Status = gBS->HandleProtocol (
+gST->ConsoleOutHandle,
+,
+(VOID **)
+);
+ }
+ if (EFI_ERROR (Status)) {
+return EFI_UNSUPPORTED;
+ }
+
+ SizeOfX = 0;
+ SizeOfY = 0;
+ if (GraphicsOutput != NULL) {
+SizeOfX = GraphicsOutput->Mode->Info->HorizontalResolution;
+SizeOfY = GraphicsOutput->Mode->Info->VerticalResolution;
+ } else if (UgaDraw != NULL) {
+Status = UgaDraw->GetMode (
+UgaDraw,
+,
+,
+,
+
+);
+if (EFI_ERROR (Status)) {
+ return EFI_UNSUPPORTED;
+}
+ } else {
+return EFI_UNSUPPORTED;
+ }
+
+ BlockWidth =
[edk2-devel] [PATCH 04/15] [platforms/devel-riscv]: RiscV/Include: Initial version of header files in RISC-V platform package
FirmwareContextProcessorSpecificLib.h - The difinitions of Firmware Context EDK2 implementaion based on RISC-V OpenSBI. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Gilbert Chen --- .../Library/FirmwareContextProcessorSpecificLib.h | 47 ++ 1 file changed, 47 insertions(+) create mode 100644 Platform/RiscV/Include/Library/FirmwareContextProcessorSpecificLib.h diff --git a/Platform/RiscV/Include/Library/FirmwareContextProcessorSpecificLib.h b/Platform/RiscV/Include/Library/FirmwareContextProcessorSpecificLib.h new file mode 100644 index 000..3bfd39f --- /dev/null +++ b/Platform/RiscV/Include/Library/FirmwareContextProcessorSpecificLib.h @@ -0,0 +1,47 @@ + +/** @file + Firmware Context Processor-specific common library + + Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved. + + This program and the accompanying materials are licensed and made available under + the terms and conditions of the BSD License that accompanies this distribution. + The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ +#ifndef __FIRMWARE_CONTEXT_PROCESSOR_SPECIFIC_LIB_H__ +#define __FIRMWARE_CONTEXT_PROCESSOR_SPECIFIC_LIB_H__ + +#include + +/** + Build up common firmware context processor-specific information + + @param FirmwareContextHartSpecific Pointer to EFI_RISCV_FIRMWARE_CONTEXT_HART_SPECIFIC + @param ParentProcessorGuid Pointer to GUID of Processor which contains this core + @param ParentProcessorUid Unique ID of pysical processor which owns this core. + @param CoreGuid Pointer to GUID of core + @param HartId Hart ID of this core. + @param IsBootHart This is boot hart or not + @param ProcessorSpecDataHob Pointer to RISC_V_PROCESSOR_SPECIFIC_DATA_HOB + + @return EFI_STATUS + +**/ +EFI_STATUS +EFIAPI +CommonFirmwareContextHartSpecificInfo ( + EFI_RISCV_FIRMWARE_CONTEXT_HART_SPECIFIC *FirmwareContextHartSpecific, + EFI_GUID *ParentProcessorGuid, + UINTN ParentProcessorUid, + EFI_GUID *CoreGuid, + UINTN HartId, + BOOLEAN IsBootHart, + RISC_V_PROCESSOR_SPECIFIC_DATA_HOB *ProcessorSpecDataHob + ); + +#endif -- 2.7.4 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#46447): https://edk2.groups.io/g/devel/message/46447 Mute This Topic: https://groups.io/mt/33044353/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
[edk2-devel] [PATCH 02/15] [platforms/devel-riscv]: Silicon/SiFive: Add library module of SiFive RISC-V cores
Initial version of SiFive RISC-V core libraries. Library of each core creates
processor core SMBIOS data hob for building SMBIOS records in DXE phase.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Gilbert Chen
---
.../E51/Library/PeiCoreInfoHobLib/CoreInfoHob.c| 248 +
.../PeiCoreInfoHobLib/PeiCoreInfoHobLib.inf| 57
.../U54/Library/PeiCoreInfoHobLib/CoreInfoHob.c| 300 +
.../PeiCoreInfoHobLib/PeiCoreInfoHobLib.inf| 57
.../Library/PeiCoreInfoHobLib/CoreInfoHob.c| 191 +
.../PeiCoreInfoHobLib/PeiCoreInfoHobLib.inf| 56
6 files changed, 909 insertions(+)
create mode 100644 Silicon/SiFive/E51/Library/PeiCoreInfoHobLib/CoreInfoHob.c
create mode 100644
Silicon/SiFive/E51/Library/PeiCoreInfoHobLib/PeiCoreInfoHobLib.inf
create mode 100644 Silicon/SiFive/U54/Library/PeiCoreInfoHobLib/CoreInfoHob.c
create mode 100644
Silicon/SiFive/U54/Library/PeiCoreInfoHobLib/PeiCoreInfoHobLib.inf
create mode 100644
Silicon/SiFive/U54MCCoreplex/Library/PeiCoreInfoHobLib/CoreInfoHob.c
create mode 100644
Silicon/SiFive/U54MCCoreplex/Library/PeiCoreInfoHobLib/PeiCoreInfoHobLib.inf
diff --git a/Silicon/SiFive/E51/Library/PeiCoreInfoHobLib/CoreInfoHob.c
b/Silicon/SiFive/E51/Library/PeiCoreInfoHobLib/CoreInfoHob.c
new file mode 100644
index 000..1009b1e
--- /dev/null
+++ b/Silicon/SiFive/E51/Library/PeiCoreInfoHobLib/CoreInfoHob.c
@@ -0,0 +1,248 @@
+/**@file
+ Build up platform processor information.
+
+ Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights
reserved.
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD
License
+ which accompanies this distribution. The full text of the license may be
found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+//
+// The package level header files this module uses
+//
+#include
+
+//
+// The Library classes this module consumes
+//
+#include
+#include
+#include
+#include
+#include
+
+#include
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+/**
+ Function to build core specific information HOB. RISC-V SMBIOS DXE driver
collect
+ this information and build SMBIOS Type44.
+
+ @param ParentProcessorGuidParent processor od this core.
ParentProcessorGuid
+ could be the same as CoreGuid if one
processor has
+ only one core.
+ @param ParentProcessorUid Unique ID of pysical processor which owns
this core.
+ @param HartId Hart ID of this core.
+ @param IsBootHart TRUE means this is the boot HART.
+ @param GuidHobDataPointer to receive EFI_HOB_GUID_TYPE.
+
+ @return EFI_SUCCESS The PEIM initialized successfully.
+
+**/
+EFI_STATUS
+EFIAPI
+CreateE51CoreProcessorSpecificDataHob (
+ IN EFI_GUID *ParentProcessorGuid,
+ IN UINTN ParentProcessorUid,
+ IN UINTN HartId,
+ IN BOOLEAN IsBootHart,
+ OUT RISC_V_PROCESSOR_SPECIFIC_DATA_HOB **GuidHobData
+ )
+{
+ RISC_V_PROCESSOR_SPECIFIC_DATA_HOB *CoreGuidHob;
+ EFI_GUID *ProcessorSpecDataHobGuid;
+ RISC_V_PROCESSOR_SPECIFIC_DATA_HOB ProcessorSpecDataHob;
+ struct sbi_scratch *ThisHartSbiScratch;
+ struct sbi_platform *ThisHartSbiPlatform;
+ EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT *FirmwareContext;
+ EFI_RISCV_FIRMWARE_CONTEXT_HART_SPECIFIC *FirmwareContextHartSpecific;
+
+ DEBUG ((EFI_D_INFO, "%a: Entry.\n", __FUNCTION__));
+
+ if (GuidHobData == NULL) {
+return EFI_INVALID_PARAMETER;
+ }
+
+ ThisHartSbiScratch = sbi_hart_id_to_scratch (sbi_scratch_thishart_ptr(),
(UINT32)HartId);
+ DEBUG ((EFI_D_INFO, "SBI Scratch is at 0x%x.\n", ThisHartSbiScratch));
+ ThisHartSbiPlatform = (struct sbi_platform
*)sbi_platform_ptr(ThisHartSbiScratch);
+ DEBUG ((EFI_D_INFO, "SBI platform is at 0x%x.\n", ThisHartSbiPlatform));
+ FirmwareContext = (EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT
*)ThisHartSbiPlatform->firmware_context;
+ DEBUG ((EFI_D_INFO, "Firmware Context is at 0x%x.\n", FirmwareContext));
+ FirmwareContextHartSpecific = FirmwareContext->HartSpecific[HartId];
+ DEBUG ((EFI_D_INFO, "Firmware Context Hart specific is at 0x%x.\n",
FirmwareContextHartSpecific));
+
+ //
+ // Build up RISC_V_PROCESSOR_SPECIFIC_DATA_HOB.
+ //
+ CommonFirmwareContextHartSpecificInfo (
+ FirmwareContextHartSpecific,
+ ParentProcessorGuid,
+ ParentProcessorUid,
+ (EFI_GUID *)PcdGetPtr (PcdSiFiveE51CoreGuid),
+ HartId,
+ IsBootHart,
+
+ );
+ ProcessorSpecDataHob.ProcessorSpecificData.MModeExcepDelegation.Value64_L
= TO_BE_FILLED;
+
[edk2-devel] [PATCH 06/15] [platforms/devel-riscv]: RiscV/Universal: Initial version of common RISC-V SEC module
Common RISC-V SEC module for RISC-V platforms. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Gilbert Chen --- Platform/RiscV/Universal/Sec/Riscv64/SecEntry.s | 439 Platform/RiscV/Universal/Sec/SecMain.c | 529 Platform/RiscV/Universal/Sec/SecMain.h | 56 +++ Platform/RiscV/Universal/Sec/SecMain.inf| 81 4 files changed, 1105 insertions(+) create mode 100644 Platform/RiscV/Universal/Sec/Riscv64/SecEntry.s create mode 100644 Platform/RiscV/Universal/Sec/SecMain.c create mode 100644 Platform/RiscV/Universal/Sec/SecMain.h create mode 100644 Platform/RiscV/Universal/Sec/SecMain.inf diff --git a/Platform/RiscV/Universal/Sec/Riscv64/SecEntry.s b/Platform/RiscV/Universal/Sec/Riscv64/SecEntry.s new file mode 100644 index 000..a5ca481 --- /dev/null +++ b/Platform/RiscV/Universal/Sec/Riscv64/SecEntry.s @@ -0,0 +1,439 @@ +/* + * Copyright (c) 2019 , Hewlett Packard Enterprise Development LP. All rights reserved. + * + * SPDX-License-Identifier: BSD-2-Clause + * + * Copyright (c) 2019 Western Digital Corporation or its affiliates. + * + * Authors: + * Anup Patel + * + */ + +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +.text +.align 3 +.global ASM_PFX(_ModuleEntryPoint) +ASM_PFX(_ModuleEntryPoint): + /* + * Jump to warm-boot if this is not the selected core booting, + */ + csrr a6, CSR_MHARTID + li a5, FixedPcdGet32 (PcdBootHartId) + bne a6, a5, _wait_for_boot_hart + + // light LED on + li a5, 0x54002000 + li a4, 0xff + sw a4, 0x08(a5) + li a4, 0x11 + sw a4, 0x0c(a5) + + lira, 0 + call_reset_regs + + /* Preload HART details + * s7 -> HART Count + * s8 -> HART Stack Size + */ + li s7, FixedPcdGet32 (PcdHartCount) + li s8, FixedPcdGet32 (PcdOpenSbiStackSize) + + /* Setup scratch space for all the HARTs*/ + li tp, FixedPcdGet32 (PcdScratchRamBase) + mula5, s7, s8 + addtp, tp, a5 + /* Keep a copy of tp */ + addt3, tp, zero + /* Counter */ + lit2, 1 + /* hartid 0 is mandated by ISA */ + lit1, 0 +_scratch_init: + addtp, t3, zero + mula5, s8, t1 + subtp, tp, a5 + lia5, SBI_SCRATCH_SIZE + subtp, tp, a5 + + /* Initialize scratch space */ + li a4, FixedPcdGet32 (PcdFwStartAddress) + li a5, FixedPcdGet32 (PcdFwEndAddress) + suba5, a5, a4 + sda4, SBI_SCRATCH_FW_START_OFFSET(tp) + sda5, SBI_SCRATCH_FW_SIZE_OFFSET(tp) + /* Note: fw_next_arg1() uses a0, a1, and ra */ + callfw_next_arg1 + sda0, SBI_SCRATCH_NEXT_ARG1_OFFSET(tp) + /* Note: fw_next_addr() uses a0, a1, and ra */ + callfw_next_addr + sda0, SBI_SCRATCH_NEXT_ADDR_OFFSET(tp) + lia4, PRV_S + sda4, SBI_SCRATCH_NEXT_MODE_OFFSET(tp) + laa4, _start_warm + sda4, SBI_SCRATCH_WARMBOOT_ADDR_OFFSET(tp) + laa4, platform + sda4, SBI_SCRATCH_PLATFORM_ADDR_OFFSET(tp) + laa4, _hartid_to_scratch + sda4, SBI_SCRATCH_HARTID_TO_SCRATCH_OFFSET(tp) + sdzero, SBI_SCRATCH_TMP0_OFFSET(tp) +#ifdef FW_OPTIONS + lia4, FW_OPTIONS + sda4, SBI_SCRATCH_OPTIONS_OFFSET(tp) +#else + sdzero, SBI_SCRATCH_OPTIONS_OFFSET(tp) +#endif + addt1, t1, t2 + bltt1, s7, _scratch_init + + /* Fill-out temporary memory with 55aa*/ + lia4, FixedPcdGet32 (PcdTemporaryRamBase) + lia5, FixedPcdGet32 (PcdTemporaryRamSize) + add a5, a4, a5 +1: + li a3, 0x5AA55AA55AA55AA5 + sda3, (a4) + adda4, a4, __SIZEOF_POINTER__ + blta4, a5, 1b + + /* Update boot hart flag */ + laa4, _boot_hart_done + lia5, 1 + sda5, (a4) + + /* Wait for boot hart */ +_wait_for_boot_hart: + laa4, _boot_hart_done + lda5, (a4) + /* Reduce the bus traffic so that boot hart may proceed faster */ + nop + nop + nop + beqza5, _wait_for_boot_hart + +_start_warm: + lira, 0 + call_reset_regs + + /* Disable and clear all interrupts */ + csrwCSR_MIE, zero + csrwCSR_MIP, zero + + li s7, FixedPcdGet32 (PcdHartCount) + li s8, FixedPcdGet32 (PcdOpenSbiStackSize) + + /* HART ID should be within expected limit */ + csrrs6, CSR_MHARTID + bges6, s7, _start_hang + + /* find the scratch space for this hart */ + litp, FixedPcdGet32 (PcdScratchRamBase) + mula5, s7, s8 + addtp, tp, a5 + mula5, s8, s6 + subtp, tp, a5 + lia5, SBI_SCRATCH_SIZE + subtp, tp, a5 + + /* update the mscratch */ + csrwCSR_MSCRATCH, tp + + /*make room for Hart specific Firmware Context*/ + lia5, FIRMWARE_CONTEXT_HART_SPECIFIC_SIZE + subtp, tp, a5 + + /* Setup stack */ + add sp, tp, zero + + /* Setup stack for the Hart executing EFI to top of temporary ram*/ + csrr a6, CSR_MHARTID + li a5, FixedPcdGet32 (PcdBootHartId) + bne a6, a5, 1f + + li a4, FixedPcdGet32(PcdTemporaryRamBase) + li a5, FixedPcdGet32(PcdTemporaryRamSize) + addsp, a4, a5 + 1: + + /* Setup trap handler */ + laa4, _trap_handler + csrwCSR_MTVEC, a4 + /* Make sure that mtvec is updated */ + 1: + csrra5, CSR_MTVEC + bnea4, a5, 1b + + /* Call library constructors before jup to SEC core */ + call ProcessLibraryConstructorList + + /* jump to SEC
[edk2-devel] [PATCH 11/15] [platforms/devel-riscv]: U500Pkg/Library: Library instances of U500 platform library.
PeiCoreInfoHobLib
- This is the library to create RISC-V core characteristics for building up
RISC-V related SMBIOS records to support the unified boot loader and OS image.
- RiscVPlatformTimerLib
This is U500 platform timer library which has the platform-specific timer
implementation.
- SerialPortLib
U500 serial port platform library
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Gilbert Chen
---
.../Library/PeiCoreInfoHobLib/CoreInfoHob.c| 201 +
.../PeiCoreInfoHobLib/PeiCoreInfoHobLib.inf| 64 ++
.../RiscVPlatformTimerLib.inf | 46
.../RiscVPlatformTimerLib/RiscVPlatformTimerLib.s | 54 +
.../U500Pkg/Library/SerialIoLib/SerialIoLib.inf| 37 +++
.../U500Pkg/Library/SerialIoLib/SerialPortLib.c| 247 +
.../Library/SerialIoLib/U500SerialPortLib.uni | 22 ++
7 files changed, 671 insertions(+)
create mode 100644
Platform/RiscV/SiFive/U500Pkg/Library/PeiCoreInfoHobLib/CoreInfoHob.c
create mode 100644
Platform/RiscV/SiFive/U500Pkg/Library/PeiCoreInfoHobLib/PeiCoreInfoHobLib.inf
create mode 100644
Platform/RiscV/SiFive/U500Pkg/Library/RiscVPlatformTimerLib/RiscVPlatformTimerLib.inf
create mode 100644
Platform/RiscV/SiFive/U500Pkg/Library/RiscVPlatformTimerLib/RiscVPlatformTimerLib.s
create mode 100644
Platform/RiscV/SiFive/U500Pkg/Library/SerialIoLib/SerialIoLib.inf
create mode 100644
Platform/RiscV/SiFive/U500Pkg/Library/SerialIoLib/SerialPortLib.c
create mode 100644
Platform/RiscV/SiFive/U500Pkg/Library/SerialIoLib/U500SerialPortLib.uni
diff --git
a/Platform/RiscV/SiFive/U500Pkg/Library/PeiCoreInfoHobLib/CoreInfoHob.c
b/Platform/RiscV/SiFive/U500Pkg/Library/PeiCoreInfoHobLib/CoreInfoHob.c
new file mode 100644
index 000..2db4fdc
--- /dev/null
+++ b/Platform/RiscV/SiFive/U500Pkg/Library/PeiCoreInfoHobLib/CoreInfoHob.c
@@ -0,0 +1,201 @@
+/**@file
+ Build up platform processor information.
+
+ Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights
reserved.
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD
License
+ which accompanies this distribution. The full text of the license may be
found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+//
+// The package level header files this module uses
+//
+#include
+
+//
+// The Library classes this module consumes
+//
+#include
+#include
+#include
+
+#include
+#include
+#include
+#include
+#include
+
+/**
+ Build up processor-specific HOB for U5MC Coreplex
+
+ @param UniqueId Unique ID of this U5MC Coreplex processor
+
+ @return EFI_SUCCESS The PEIM initialized successfully.
+
+**/
+EFI_STATUS
+EFIAPI
+CreateU5MCCoreplexProcessorSpecificDataHob (
+ IN UINTN UniqueId
+ )
+{
+ EFI_STATUS Status;
+ UINT32 HartIdNumber;
+ RISC_V_PROCESSOR_SPECIFIC_DATA_HOB *GuidHobData;
+ EFI_GUID *ParentCoreGuid;
+ BOOLEAN MCSupport;
+
+ DEBUG ((EFI_D_INFO, "Building U5 Coreplex processor information HOB\n"));
+
+ HartIdNumber = 0;
+ ParentCoreGuid = PcdGetPtr(PcdSiFiveU5MCCoreplexGuid);
+ MCSupport = PcdGetBool (PcdE5MCSupported);
+ if (MCSupport == TRUE) {
+Status = CreateE51CoreProcessorSpecificDataHob (ParentCoreGuid, UniqueId,
HartIdNumber, FALSE, );
+if (EFI_ERROR (Status)) {
+ DEBUG ((EFI_D_ERROR, "Faile to build U5MC processor informatino HOB\n"));
+ ASSERT (FALSE);
+}
+HartIdNumber ++;
+DEBUG ((EFI_D_INFO, "Support E5 Monitor core on U500 platform, HOB at
address 0x%x\n", GuidHobData));
+ }
+ for (; HartIdNumber < (FixedPcdGet32 (PcdNumberofU5Cores) +
(UINT32)MCSupport); HartIdNumber ++) {
+Status = CreateU54CoreProcessorSpecificDataHob (ParentCoreGuid, UniqueId,
HartIdNumber, (HartIdNumber == FixedPcdGet32 (PcdBootHartId))? TRUE: FALSE,
);
+if (EFI_ERROR (Status)) {
+ DEBUG ((EFI_D_ERROR, "Faile to build U5MC processor informatino HOB\n"));
+ ASSERT (FALSE);
+}
+DEBUG ((EFI_D_INFO, "Support U5 application core on U500 platform, HOB
Data at address 0x%x\n", GuidHobData));
+ }
+ DEBUG ((EFI_D_INFO, "Support %d U5 application cores on U500 platform\n",
HartIdNumber - (UINT32)MCSupport));
+
+ if (HartIdNumber != FixedPcdGet32 (PcdHartCount)) {
+DEBUG ((EFI_D_ERROR, "Improper core settings...\n"));
+DEBUG ((EFI_D_ERROR, "PcdHartCount\n"));
+DEBUG ((EFI_D_ERROR, "PcdNumberofU5Cores\n"));
+DEBUG ((EFI_D_ERROR, "PcdE5MCSupported\n\n"));
+ASSERT (FALSE);
+ }
+ return Status;
+}
+
+/**
+ Function to build processor related SMBIOS information. RISC-V SMBIOS DXE
driver collect
+ this information and build SMBIOS Type4 and Type7 record.
+
+ @param ProcessorUidUnique ID of pysical processor which owns this core.
+ @param
[edk2-devel] [PATCH 10/15] [platforms/devel-riscv]: U500Pkg/Library: Library instances of U500 platform library.
OpneSbiPlatformLib
- In order to reduce the dependencies with RISC-V OpenSBI project
(https://github.com/riscv/opensbi) and less burdens to EDK2 build process, the
implementation of RISC-V EDK2 platform is leverage platform source code from
OpenSBI code tree. The "platform.c" under OpenSbiPlatformLib is cloned from
RISC-V OpenSBI code tree (in EDK2 RiscVPkg) and built based on EDK2 build
environment.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Gilbert Chen
---
.../OpenSbiPlatformLib/OpenSbiPlatformLib.inf | 53 +
.../U500Pkg/Library/OpenSbiPlatformLib/platform.c | 214 +
2 files changed, 267 insertions(+)
create mode 100644
Platform/RiscV/SiFive/U500Pkg/Library/OpenSbiPlatformLib/OpenSbiPlatformLib.inf
create mode 100644
Platform/RiscV/SiFive/U500Pkg/Library/OpenSbiPlatformLib/platform.c
diff --git
a/Platform/RiscV/SiFive/U500Pkg/Library/OpenSbiPlatformLib/OpenSbiPlatformLib.inf
b/Platform/RiscV/SiFive/U500Pkg/Library/OpenSbiPlatformLib/OpenSbiPlatformLib.inf
new file mode 100644
index 000..1823e48
--- /dev/null
+++
b/Platform/RiscV/SiFive/U500Pkg/Library/OpenSbiPlatformLib/OpenSbiPlatformLib.inf
@@ -0,0 +1,53 @@
+## @file
+# RISC-V OpenSbi Platform Library
+# This is the the required library which provides platform
+# level opensbi functions follow RISC-V opensbi implementation.
+#
+# Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights
reserved.
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD
License
+# which accompanies this distribution. The full text of the license may be
found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR
IMPLIED.
+#
+##
+
+[Defines]
+ INF_VERSION= 0x00010005
+ BASE_NAME = OpenSbiPlatformLib
+ FILE_GUID = 9424ED54-EBDA-4FB5-8FF6-8291B07BB151
+ MODULE_TYPE= SEC
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = OpenSbiPlatformLib
+
+#
+# The following information is for reference only and not required by the
build tools.
+#
+# VALID_ARCHITECTURES = RISCV64 EBC
+#
+
+[Sources]
+ platform.c
+
+[Packages]
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ RiscVPkg/RiscVPkg.dec
+ Platform/RiscV/RiscVPlatformPkg.dec
+
+[LibraryClasses]
+ BaseLib
+ DebugLib
+ BaseMemoryLib
+ PcdLib
+ DebugAgentLib
+ RiscVCpuLib
+ PrintLib
+
+[FixedPcd]
+ gUefiRiscVPlatformPkgTokenSpaceGuid.PcdHartCount
+ gUefiRiscVPlatformPkgTokenSpaceGuid.PcdOpenSbiStackSize
+ gUefiRiscVPlatformPkgTokenSpaceGuid.PcdBootHartId
diff --git
a/Platform/RiscV/SiFive/U500Pkg/Library/OpenSbiPlatformLib/platform.c
b/Platform/RiscV/SiFive/U500Pkg/Library/OpenSbiPlatformLib/platform.c
new file mode 100644
index 000..887a279
--- /dev/null
+++ b/Platform/RiscV/SiFive/U500Pkg/Library/OpenSbiPlatformLib/platform.c
@@ -0,0 +1,214 @@
+/*
+ * SPDX-License-Identifier: BSD-2-Clause
+ *
+ * Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights
reserved.
+ * Copyright (c) 2019 Western Digital Corporation or its affiliates.
+ *
+ * Authors:
+ * Atish Patra
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+
+#define U500_HART_COUNTFixedPcdGet32(PcdHartCount)
+#define U500_HART_STACK_SIZEFixedPcdGet32(PcdOpenSbiStackSize)
+#define U500_BOOT_HART_ID FixedPcdGet32(PcdBootHartId)
+
+#define U500_SYS_CLK1
+
+#define U500_CLINT_ADDR0x200
+
+#define U500_PLIC_ADDR0xc00
+#define U500_PLIC_NUM_SOURCES0x35
+#define U500_PLIC_NUM_PRIORITIES7
+
+#define U500_UART_ADDR0x5400
+
+#define U500_UART_BAUDRATE115200
+
+/**
+ * The U500 SoC has 8 HARTs but HART ID 0 doesn't have S mode.
+ * HARTs 1 is selected as boot HART
+ */
+#ifndef U500_ENABLED_HART_MASK
+#define U500_ENABLED_HART_MASK(1 << U500_BOOT_HART_ID)
+#endif
+
+#define U500_HARTID_DISABLED~(U500_ENABLED_HART_MASK)
+
+/* PRCI clock related macros */
+//TODO: Do we need a separate driver for this ?
+#define U500_PRCI_BASE_ADDR0x1000
+#define U500_PRCI_CLKMUXSTATUSREG0x002C
+#define U500_PRCI_CLKMUX_STATUS_TLCLKSEL(0x1 << 1)
+
+static void U500_modify_dt(void *fdt)
+{
+u32 i, size;
+int chosen_offset, err;
+int cpu_offset;
+char cpu_node[32] = "";
+const char *mmu_type;
+
+for (i = 0; i < U500_HART_COUNT; i++) {
+sbi_sprintf(cpu_node, "/cpus/cpu@%d", i);
+cpu_offset = fdt_path_offset(fdt, cpu_node);
+mmu_type = fdt_getprop(fdt, cpu_offset, "mmu-type", NULL);
+if (mmu_type && (!strcmp(mmu_type, "riscv,sv39") ||
+!strcmp(mmu_type,"riscv,sv48")))
+continue;
+else
+fdt_setprop_string(fdt, cpu_offset, "status", "masked");
+memset(cpu_node, 0, sizeof(cpu_node));
+}
+size =
[edk2-devel] [PATCH 15/15] [platforms/devel-riscv]: Platforms: Readme file updates
Update Readme.md and Maintainers.txt for RISV-V platforms. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Gilbert Chen --- Maintainers.txt | 9 + Readme.md | 5 + 2 files changed, 14 insertions(+) diff --git a/Maintainers.txt b/Maintainers.txt index 876ae56..c494c9d 100644 --- a/Maintainers.txt +++ b/Maintainers.txt @@ -108,6 +108,11 @@ R: Marcin Wojtas Platform/SolidRun/Armada80x0McBin R: Marcin Wojtas +Platform/RiscV +Platform/RiscV/SiFive/U500Pkg +R: Abner Chang +R: Gilbert Chen + Silicon M: Ard Biesheuvel M: Leif Lindholm @@ -151,3 +156,7 @@ M: Liming Gao Silicon/Marvell R: Marcin Wojtas + +Silicon/SiFive +R: Abner Chang +R: Gilbert Chen diff --git a/Readme.md b/Readme.md index 63e59f6..4572d19 100644 --- a/Readme.md +++ b/Readme.md @@ -52,6 +52,7 @@ ARM | arm-linux-gnueabihf- IA32| i?86-linux-gnu-* _or_ x86_64-linux-gnu- IPF | ia64-linux-gnu X64 | x86_64-linux-gnu- +RISCV64 | riscv64-unknown-elf- \* i386, i486, i586 or i686 @@ -243,6 +244,10 @@ For more information, see the ## Raspberry Pi * [Pi 3](Platform/RaspberryPi/RPi3) +## RISC-V +### SiFive +* [Freedom U500 VC707 FPGA](Platform/RiscV/SiFive/U500Pkg) + ## Socionext * [SynQuacer](Platform/Socionext/DeveloperBox) -- 2.7.4 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#46433): https://edk2.groups.io/g/devel/message/46433 Mute This Topic: https://groups.io/mt/33044344/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
[edk2-devel] [PATCH 05/15] [platforms/devel-riscv]: RiscV/Library: Initial version of libraries introduced in RISC-V platform package
FirmwareContextProcessorSpecificLib
- Common library to consume EFI_RISCV_FIRMWARE_CONTEXT_HART_SPECIFIC and build
up processor specific data HOB.
RealTimClockLibNull
- NULL instance of Real Time Clock library.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Gilbert Chen
---
.../FirmwareContextProcessorSpecificLib.c | 88 +
.../FirmwareContextProcessorSpecificLib.inf| 39
.../RealTimeClockLibNull/RealTimeClockLibNull.c| 212 +
.../RealTimeClockLibNull/RealTimeClockLibNull.inf | 36
4 files changed, 375 insertions(+)
create mode 100644
Platform/RiscV/Library/FirmwareContextProcessorSpecificLib/FirmwareContextProcessorSpecificLib.c
create mode 100644
Platform/RiscV/Library/FirmwareContextProcessorSpecificLib/FirmwareContextProcessorSpecificLib.inf
create mode 100644
Platform/RiscV/Library/RealTimeClockLibNull/RealTimeClockLibNull.c
create mode 100644
Platform/RiscV/Library/RealTimeClockLibNull/RealTimeClockLibNull.inf
diff --git
a/Platform/RiscV/Library/FirmwareContextProcessorSpecificLib/FirmwareContextProcessorSpecificLib.c
b/Platform/RiscV/Library/FirmwareContextProcessorSpecificLib/FirmwareContextProcessorSpecificLib.c
new file mode 100644
index 000..0ce2570
--- /dev/null
+++
b/Platform/RiscV/Library/FirmwareContextProcessorSpecificLib/FirmwareContextProcessorSpecificLib.c
@@ -0,0 +1,88 @@
+/**@file
+ Common library to build upfirmware context processor-specific information
+
+ Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights
reserved.
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD
License
+ which accompanies this distribution. The full text of the license may be
found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+//
+// The package level header files this module uses
+//
+#include
+
+//
+// The Library classes this module consumes
+//
+#include
+#include
+#include
+
+#include
+#include
+#include
+#include
+#include
+#include
+
+/**
+ Build up common firmware context processor-specific information
+
+ @param FirmwareContextHartSpecific Pointer to
EFI_RISCV_FIRMWARE_CONTEXT_HART_SPECIFIC
+ @param ParentProcessorGuid Pointer to GUID of Processor which
contains this core
+ @param ParentProcessorUid Unique ID of pysical processor which
owns this core.
+ @param CoreGuid Pointer to GUID of core
+ @param HartId Hart ID of this core.
+ @param IsBootHart This is boot hart or not
+ @param ProcessorSpecDataHob Pointer to
RISC_V_PROCESSOR_SPECIFIC_DATA_HOB
+
+ @return EFI_STATUS
+
+**/
+EFI_STATUS
+EFIAPI
+CommonFirmwareContextHartSpecificInfo (
+ EFI_RISCV_FIRMWARE_CONTEXT_HART_SPECIFIC *FirmwareContextHartSpecific,
+ EFI_GUID *ParentProcessorGuid,
+ UINTN ParentProcessorUid,
+ EFI_GUID *CoreGuid,
+ UINTN HartId,
+ BOOLEAN IsBootHart,
+ RISC_V_PROCESSOR_SPECIFIC_DATA_HOB *ProcessorSpecDataHob
+ )
+{
+ //
+ // Build up RISC_V_PROCESSOR_SPECIFIC_DATA_HOB.
+ //
+ CopyGuid (>ParentPrcessorGuid, ParentProcessorGuid);
+ ProcessorSpecDataHob->ParentProcessorUid = ParentProcessorUid;
+ CopyGuid (>CoreGuid, CoreGuid);
+ ProcessorSpecDataHob->Context = NULL;
+ ProcessorSpecDataHob->ProcessorSpecificData.Revision =
SMBIOS_RISC_V_PROCESSOR_SPECIFIC_DATA_REVISION;
+ ProcessorSpecDataHob->ProcessorSpecificData.Length = sizeof
(SMBIOS_RISC_V_PROCESSOR_SPECIFIC_DATA);
+ ProcessorSpecDataHob->ProcessorSpecificData.HartId.Value64_L =
(UINT64)HartId;
+ ProcessorSpecDataHob->ProcessorSpecificData.HartId.Value64_H = 0;
+ ProcessorSpecDataHob->ProcessorSpecificData.BootHartId =
(UINT8)IsBootHart;
+ ProcessorSpecDataHob->ProcessorSpecificData.InstSetSupported =
FirmwareContextHartSpecific->IsaExtensionSupported;
+ ProcessorSpecDataHob->ProcessorSpecificData.PrivilegeModeSupported =
SMBIOS_RISC_V_PSD_MACHINE_MODE_SUPPORTED;
+ if ((ProcessorSpecDataHob->ProcessorSpecificData.InstSetSupported &
RISC_V_ISA_SUPERVISOR_MODE_IMPLEMENTED) != 0) {
+ProcessorSpecDataHob->ProcessorSpecificData.PrivilegeModeSupported |=
SMBIOS_RISC_V_PSD_SUPERVISOR_MODE_SUPPORTED;
+ }
+ if ((ProcessorSpecDataHob->ProcessorSpecificData.InstSetSupported &
RISC_V_ISA_USER_MODE_IMPLEMENTED) != 0) {
+ProcessorSpecDataHob->ProcessorSpecificData.PrivilegeModeSupported |=
SMBIOS_RISC_V_PSD_USER_MODE_SUPPORTED;
+ }
+ ProcessorSpecDataHob->ProcessorSpecificData.MachineVendorId.Value64_L =
FirmwareContextHartSpecific->MachineVendorId.Value64_L;
+ ProcessorSpecDataHob->ProcessorSpecificData.MachineVendorId.Value64_H =
FirmwareContextHartSpecific->MachineVendorId.Value64_H;
+
[edk2-devel] [PATCH 07/15] [platforms/devel-riscv]: RiscV/SiFive: Initial version of SiFive U500 platform package
The initial version of SiFive U500 platform package.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Gilbert Chen
---
Platform/RiscV/SiFive/U500Pkg/Readme.md| 30 ++
Platform/RiscV/SiFive/U500Pkg/U500.dec | 40 ++
Platform/RiscV/SiFive/U500Pkg/U500.dsc | 596 +
Platform/RiscV/SiFive/U500Pkg/U500.fdf | 373
Platform/RiscV/SiFive/U500Pkg/U500.fdf.inc | 58 +++
Platform/RiscV/SiFive/U500Pkg/U500.uni | Bin 0 -> 1730 bytes
Platform/RiscV/SiFive/U500Pkg/U500PkgExtra.uni | Bin 0 -> 1396 bytes
Platform/RiscV/SiFive/U500Pkg/VarStore.fdf.inc | 85
8 files changed, 1182 insertions(+)
create mode 100644 Platform/RiscV/SiFive/U500Pkg/Readme.md
create mode 100644 Platform/RiscV/SiFive/U500Pkg/U500.dec
create mode 100644 Platform/RiscV/SiFive/U500Pkg/U500.dsc
create mode 100644 Platform/RiscV/SiFive/U500Pkg/U500.fdf
create mode 100644 Platform/RiscV/SiFive/U500Pkg/U500.fdf.inc
create mode 100644 Platform/RiscV/SiFive/U500Pkg/U500.uni
create mode 100644 Platform/RiscV/SiFive/U500Pkg/U500PkgExtra.uni
create mode 100644 Platform/RiscV/SiFive/U500Pkg/VarStore.fdf.inc
diff --git a/Platform/RiscV/SiFive/U500Pkg/Readme.md
b/Platform/RiscV/SiFive/U500Pkg/Readme.md
new file mode 100644
index 000..3aaaf77
--- /dev/null
+++ b/Platform/RiscV/SiFive/U500Pkg/Readme.md
@@ -0,0 +1,30 @@
+# Introduction
+
+## U500 Platform Package
+This is a sample RISC-V EDK2 platform package used agaist SiFive Freedom U500
VC707 FPGA Dev Kit, please refer to "SiFive Freedom U500 VC707 FPGA Getting
Started Guide" on https://www.sifive.com/documentation. This package is built
with below common packages,
+- **RiscVPlatformPkg**, edk2-platform/Platform/RiscV
+- **RiscVPkg**, edk2 master branch (Currently is in edk2-staging/RISC-V branch)
+
+This package provides librareis and modules which are SiFive U500 platform
implementation-specific and incorporate with common RISC-V packages mentioned
above.
+
+### OpneSbiPlatformLib
+In order to reduce the dependencies with RISC-V OpenSBI project
(https://github.com/riscv/opensbi) and less burdens to EDK2 build process, the
implementation of RISC-V EDK2 platform is leverage platform source code from
OpenSBI code tree. The "platform.c" under OpenSbiPlatformLib is cloned from
RISC-V OpenSBI code tree (in EDK2 RiscVPkg) and built based on EDK2 build
environment.
+
+### PeiCoreInfoHobLib
+This is the library to create RISC-V core characteristics for building up
RISC-V related SMBIOS records to support the unified boot loader and OS image.
This library leverage the silicon libraries provided in Silicon/SiFive.
+
+### RiscVPlatformTimerLib
+This is U500 platform timer library which has the platform-specific timer
implementation.
+
+### PlatformPei
+This is the platform-implementation specific library which is executed in
early PEI phase for platform initialization.
+
+### TimerDxe
+This is U500 platform timer DXE driver whcih has the platform-specific timer
implementation.
+
+## U500 Platform PCD settings
+
+| **PCD name** |**Usage**|
+||--|
+|PcdNumberofU5Cores| Number of U5 core enabled on U500 platform|
+|PcdE5MCSupported| Indicates whether or not the Monitor Core (E5) is supported
on U500 platform|
diff --git a/Platform/RiscV/SiFive/U500Pkg/U500.dec
b/Platform/RiscV/SiFive/U500Pkg/U500.dec
new file mode 100644
index 000..9886328
--- /dev/null
+++ b/Platform/RiscV/SiFive/U500Pkg/U500.dec
@@ -0,0 +1,40 @@
+## @file U500.dec
+# This Package provides SiFive U500 modules and libraries.
+#
+# Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights
reserved.
+#
+# This program and the accompanying materials are licensed and made available
under
+# the terms and conditions of the BSD License which accompanies this
distribution.
+# The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+##
+
+[Defines]
+ DEC_SPECIFICATION = 0x00010005
+ PACKAGE_NAME = U500
+ PACKAGE_UNI_FILE = U500.uni
+ PACKAGE_GUID = D11E9DB9-5940-4642-979D-2114342140D2
+ PACKAGE_VERSION= 1.0
+
+[Includes]
+ Include
+
+[LibraryClasses]
+
+
+[Guids]
+ gUefiRiscVPlatformU500PkgTokenSpaceGuid = {0xDFD87009, 0x27A1, 0x41DD, {
0x84, 0xB1, 0x35, 0xB4, 0xB9, 0x0D, 0x17, 0x63 }}
+
+[PcdsFixedAtBuild]
+
gUefiRiscVPlatformU500PkgTokenSpaceGuid.PcdNumberofU5Cores|0x8|UINT32|0x1000
+
gUefiRiscVPlatformU500PkgTokenSpaceGuid.PcdE5MCSupported|TRUE|BOOLEAN|0x1001
+
+[PcdsPatchableInModule]
+
+
+[UserExtensions.TianoCore."ExtraFiles"]
+ U500PkgExtra.uni
diff --git a/Platform/RiscV/SiFive/U500Pkg/U500.dsc
b/Platform/RiscV/SiFive/U500Pkg/U500.dsc
new file mode 100644
index
[edk2-devel] [PATCH 12/15] [platforms/devel-riscv]: U500Pkg/RamFvbServiceruntimeDxe: FVB driver for EFI variable.
Firmware Volume Block driver instance for ram based EFI variable on U500
platform.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Gilbert Chen
---
.../Dxe/RamFvbServicesRuntimeDxe/FvbInfo.c | 133 +++
.../FvbServicesRuntimeDxe.inf | 88 ++
.../Dxe/RamFvbServicesRuntimeDxe/FwBlockService.c | 1129
.../Dxe/RamFvbServicesRuntimeDxe/FwBlockService.h | 193
.../RamFvbServicesRuntimeDxe/FwBlockServiceDxe.c | 156 +++
.../Dxe/RamFvbServicesRuntimeDxe/RamFlash.c| 151 +++
.../Dxe/RamFvbServicesRuntimeDxe/RamFlash.h| 92 ++
.../Dxe/RamFvbServicesRuntimeDxe/RamFlashDxe.c | 26 +
8 files changed, 1968 insertions(+)
create mode 100644
Platform/RiscV/SiFive/U500Pkg/Universal/Dxe/RamFvbServicesRuntimeDxe/FvbInfo.c
create mode 100644
Platform/RiscV/SiFive/U500Pkg/Universal/Dxe/RamFvbServicesRuntimeDxe/FvbServicesRuntimeDxe.inf
create mode 100644
Platform/RiscV/SiFive/U500Pkg/Universal/Dxe/RamFvbServicesRuntimeDxe/FwBlockService.c
create mode 100644
Platform/RiscV/SiFive/U500Pkg/Universal/Dxe/RamFvbServicesRuntimeDxe/FwBlockService.h
create mode 100644
Platform/RiscV/SiFive/U500Pkg/Universal/Dxe/RamFvbServicesRuntimeDxe/FwBlockServiceDxe.c
create mode 100644
Platform/RiscV/SiFive/U500Pkg/Universal/Dxe/RamFvbServicesRuntimeDxe/RamFlash.c
create mode 100644
Platform/RiscV/SiFive/U500Pkg/Universal/Dxe/RamFvbServicesRuntimeDxe/RamFlash.h
create mode 100644
Platform/RiscV/SiFive/U500Pkg/Universal/Dxe/RamFvbServicesRuntimeDxe/RamFlashDxe.c
diff --git
a/Platform/RiscV/SiFive/U500Pkg/Universal/Dxe/RamFvbServicesRuntimeDxe/FvbInfo.c
b/Platform/RiscV/SiFive/U500Pkg/Universal/Dxe/RamFvbServicesRuntimeDxe/FvbInfo.c
new file mode 100644
index 000..bfed741
--- /dev/null
+++
b/Platform/RiscV/SiFive/U500Pkg/Universal/Dxe/RamFvbServicesRuntimeDxe/FvbInfo.c
@@ -0,0 +1,133 @@
+/**@file
+
+ Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights
reserved.
+ Copyright (c) 2006, Intel Corporation. All rights reserved.
+
+ This program and the accompanying materials are licensed and made available
+ under the terms and conditions of the BSD License which accompanies this
+ distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+ Module Name:
+
+FvbInfo.c
+
+ Abstract:
+
+Defines data structure that is the volume header found.These data is intent
+to decouple FVB driver with FV header.
+
+**/
+
+//
+// The package level header files this module uses
+//
+#include
+
+//
+// The protocols, PPI and GUID defintions for this module
+//
+#include
+//
+// The Library classes this module consumes
+//
+#include
+#include
+
+typedef struct {
+ UINT64 FvLength;
+ EFI_FIRMWARE_VOLUME_HEADER FvbInfo;
+ //
+ // EFI_FV_BLOCK_MAP_ENTRYExtraBlockMap[n];//n=0
+ //
+ EFI_FV_BLOCK_MAP_ENTRY End[1];
+} EFI_FVB_MEDIA_INFO;
+
+EFI_FVB_MEDIA_INFO mPlatformFvbMediaInfo[] = {
+ //
+ // Systen NvStorage FVB
+ //
+ {
+FixedPcdGet32 (PcdFlashNvStorageVariableSize) +
+FixedPcdGet32 (PcdFlashNvStorageFtwWorkingSize) +
+FixedPcdGet32 (PcdFlashNvStorageFtwSpareSize),
+{
+ {
+0,
+ }, // ZeroVector[16]
+ EFI_SYSTEM_NV_DATA_FV_GUID,
+ FixedPcdGet32 (PcdFlashNvStorageVariableSize) +
+ FixedPcdGet32 (PcdFlashNvStorageFtwWorkingSize) +
+ FixedPcdGet32 (PcdFlashNvStorageFtwSpareSize),
+ EFI_FVH_SIGNATURE,
+ EFI_FVB2_MEMORY_MAPPED |
+EFI_FVB2_READ_ENABLED_CAP |
+EFI_FVB2_READ_STATUS |
+EFI_FVB2_WRITE_ENABLED_CAP |
+EFI_FVB2_WRITE_STATUS |
+EFI_FVB2_ERASE_POLARITY |
+EFI_FVB2_ALIGNMENT_16,
+ sizeof (EFI_FIRMWARE_VOLUME_HEADER) + sizeof (EFI_FV_BLOCK_MAP_ENTRY),
+ 0, // CheckSum
+ 0, // ExtHeaderOffset
+ {
+0,
+ }, // Reserved[1]
+ 2, // Revision
+ {
+{
+ (FixedPcdGet32 (PcdFlashNvStorageVariableSize) +
+ FixedPcdGet32 (PcdFlashNvStorageFtwWorkingSize) +
+ FixedPcdGet32 (PcdFlashNvStorageFtwSpareSize)) /
+ FixedPcdGet32 (PcdVariableFdBlockSize),
+ FixedPcdGet32 (PcdVariableFdBlockSize),
+}
+ } // BlockMap[1]
+},
+{
+ {
+0,
+0
+ }
+} // End[1]
+ }
+};
+
+EFI_STATUS
+GetFvbInfo (
+ IN UINT64FvLength,
+ OUT EFI_FIRMWARE_VOLUME_HEADER**FvbInfo
+ )
+{
+ STATIC BOOLEAN Checksummed = FALSE;
+ UINTN Index;
+
+ if (!Checksummed) {
+for (Index = 0;
+ Index < sizeof (mPlatformFvbMediaInfo) / sizeof (EFI_FVB_MEDIA_INFO);
+ Index += 1) {
+ UINT16 Checksum;
+ mPlatformFvbMediaInfo[Index].FvbInfo.Checksum = 0;
+ Checksum =
[edk2-devel] [PATCH 08/15] [platforms/devel-riscv]: U500Pkg/Include: Header files of SiFive U500 platform
The initial header file commit for SiFive U5-MC Coreplex and U500 Core Local interrupt definitions. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Gilbert Chen --- .../SiFive/U500Pkg/Include/SiFiveU5MCCoreplex.h| 57 ++ Platform/RiscV/SiFive/U500Pkg/Include/U500Clint.h | 24 + 2 files changed, 81 insertions(+) create mode 100644 Platform/RiscV/SiFive/U500Pkg/Include/SiFiveU5MCCoreplex.h create mode 100644 Platform/RiscV/SiFive/U500Pkg/Include/U500Clint.h diff --git a/Platform/RiscV/SiFive/U500Pkg/Include/SiFiveU5MCCoreplex.h b/Platform/RiscV/SiFive/U500Pkg/Include/SiFiveU5MCCoreplex.h new file mode 100644 index 000..c0323a5 --- /dev/null +++ b/Platform/RiscV/SiFive/U500Pkg/Include/SiFiveU5MCCoreplex.h @@ -0,0 +1,57 @@ +/** @file + SiFive U54 Coreplex library definitions. + + Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved. + + This program and the accompanying materials are licensed and made available under + the terms and conditions of the BSD License that accompanies this distribution. + The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ +#ifndef __SIFIVE_U5MC_COREPLEX_H__ +#define __SIFIVE_U5MC_COREPLEX_H__ + +#include + +#include +#include + +#define SIFIVE_U5MC_COREPLEX_MC_HART_ID 0 + +/** + Build up U5MC coreplex processor core-specific information. + + @param UniqueId U5MC unique ID. + + @return EFI_STATUS + +**/ +EFI_STATUS +EFIAPI +CreateU5MCCoreplexProcessorSpecificDataHob ( + IN UINTN UniqueId + ); + +/** + Function to build processor related SMBIOS information. RISC-V SMBIOS DXE driver collect + this information and build SMBIOS Type4 and Type7 record. + + @param ProcessorUidUnique ID of pysical processor which owns this core. + @param SmbiosDataHobPtrPointer to receive RISC_V_PROCESSOR_SMBIOS_DATA_HOB. The pointers + maintained in this structure is only valid before memory is discovered. + Access to those pointers after memory is installed will cause unexpected issues. + + @return EFI_SUCCESS The PEIM initialized successfully. + +**/ +EFI_STATUS +EFIAPI +CreateU5MCProcessorSmbiosDataHob ( + IN UINTN ProcessorUid, + OUT RISC_V_PROCESSOR_SMBIOS_DATA_HOB **SmbiosDataHobPtr + ); +#endif diff --git a/Platform/RiscV/SiFive/U500Pkg/Include/U500Clint.h b/Platform/RiscV/SiFive/U500Pkg/Include/U500Clint.h new file mode 100644 index 000..426bf43 --- /dev/null +++ b/Platform/RiscV/SiFive/U500Pkg/Include/U500Clint.h @@ -0,0 +1,24 @@ +/** @file + RISC-V Timer Architectural definition for U500 platform. + + Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved. + + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +**/ +#ifndef _U500_H_ +#define _U500_H_ + +#define CLINT_REG_MTIME 0x0200BFF8 +#define CLINT_REG_MTIMECMP0 0x02004000 +#define CLINT_REG_MTIMECMP1 0x02004008 +#define CLINT_REG_MTIMECMP2 0x02004010 +#define CLINT_REG_MTIMECMP3 0x02004018 +#define CLINT_REG_MTIMECMP4 0x02004020 + +#endif \ No newline at end of file -- 2.7.4 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#46429): https://edk2.groups.io/g/devel/message/46429 Mute This Topic: https://groups.io/mt/33044340/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
[edk2-devel] [PATCH 01/15] [platforms/devel-riscv]: Silicon/SiFive: Initial version of SiFive silicon package
Add SiFive silicon EDK2 metafile and header files of SiFive RISC-V cores. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Gilbert Chen --- Silicon/SiFive/Include/Library/SiFiveE51.h | 66 ++ Silicon/SiFive/Include/Library/SiFiveU54.h | 66 ++ .../SiFive/Include/Library/SiFiveU54MCCoreplex.h | 61 Silicon/SiFive/SiFive.dec | 45 +++ 4 files changed, 238 insertions(+) create mode 100644 Silicon/SiFive/Include/Library/SiFiveE51.h create mode 100644 Silicon/SiFive/Include/Library/SiFiveU54.h create mode 100644 Silicon/SiFive/Include/Library/SiFiveU54MCCoreplex.h create mode 100644 Silicon/SiFive/SiFive.dec diff --git a/Silicon/SiFive/Include/Library/SiFiveE51.h b/Silicon/SiFive/Include/Library/SiFiveE51.h new file mode 100644 index 000..96b1082 --- /dev/null +++ b/Silicon/SiFive/Include/Library/SiFiveE51.h @@ -0,0 +1,66 @@ +/** @file + SiFive E51 Core library definitions. + + Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved. + + This program and the accompanying materials are licensed and made available under + the terms and conditions of the BSD License that accompanies this distribution. + The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ +#ifndef __SIFIVE_E51_CORE_H__ +#define __SIFIVE_E51_CORE_H__ + +#include + +#include +#include + +/** + Function to build core specific information HOB. + + @param ParentProcessorGuidParent processor od this core. ParentProcessorGuid + could be the same as CoreGuid if one processor has + only one core. + @param ParentProcessorUid Unique ID of pysical processor which owns this core. + @param HartId Hart ID of this core. + @param IsBootHart TRUE means this is the boot HART. + @param GuidHobDataPointer to receive RISC_V_PROCESSOR_SPECIFIC_DATA_HOB. + + @return EFI_SUCCESS The PEIM initialized successfully. + +**/ +EFI_STATUS +EFIAPI +CreateE51CoreProcessorSpecificDataHob ( + IN EFI_GUID *ParentProcessorGuid, + IN UINTN ParentProcessorUid, + IN UINTN HartId, + IN BOOLEAN IsBootHart, + OUT RISC_V_PROCESSOR_SPECIFIC_DATA_HOB **GuidHobData + ); + +/** + Function to build processor related SMBIOS information. RISC-V SMBIOS DXE driver collect + this information and build SMBIOS Type4 and Type7 record. + + @param ProcessorUidUnique ID of pysical processor which owns this core. + @param SmbiosHobPtrPointer to receive RISC_V_PROCESSOR_SMBIOS_DATA_HOB. The pointers + maintained in this structure is only valid before memory is discovered. + Access to those pointers after memory is installed will cause unexpected issues. + + @return EFI_SUCCESS The PEIM initialized successfully. + +**/ +EFI_STATUS +EFIAPI +CreateE51ProcessorSmbiosDataHob ( + IN UINTN ProcessorUid, + OUT RISC_V_PROCESSOR_SMBIOS_DATA_HOB **SmbiosHobPtr + ); + +#endif diff --git a/Silicon/SiFive/Include/Library/SiFiveU54.h b/Silicon/SiFive/Include/Library/SiFiveU54.h new file mode 100644 index 000..216b584 --- /dev/null +++ b/Silicon/SiFive/Include/Library/SiFiveU54.h @@ -0,0 +1,66 @@ +/** @file + SiFive U54 Core library definitions. + + Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved. + + This program and the accompanying materials are licensed and made available under + the terms and conditions of the BSD License that accompanies this distribution. + The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ +#ifndef __SIFIVE_U54_CORE_H__ +#define __SIFIVE_U54_CORE_H__ + +#include + +#include +#include + +/** + Function to build core specific information HOB. + + @param ParentProcessorGuidParent processor od this core. ParentProcessorGuid + could be the same as CoreGuid if one processor has + only one core. + @param ParentProcessorUid Unique ID of pysical processor which owns this core. + @param HartId Hart ID of this core. + @param IsBootHart TRUE means this is the boot HART. + @param GuidHobdataPointer to RISC_V_PROCESSOR_SPECIFIC_DATA_HOB. + + @return EFI_SUCCESS The PEIM initialized successfully. + +**/ +EFI_STATUS +EFIAPI +CreateU54CoreProcessorSpecificDataHob ( + IN EFI_GUID *ParentProcessorGuid, + IN UINTN
[edk2-devel] [PATCH 14/15] [platforms/devel-riscv]: U500Pkg/PlatformPei: Platform initialization PEIM
This is the platform-implementation specific library which is executed in early
PEI phase for platform initialization.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Gilbert Chen
---
.../SiFive/U500Pkg/Universal/Pei/PlatformPei/Fv.c | 55
.../U500Pkg/Universal/Pei/PlatformPei/MemDetect.c | 80 ++
.../U500Pkg/Universal/Pei/PlatformPei/Platform.c | 319 +
.../U500Pkg/Universal/Pei/PlatformPei/Platform.h | 97 +++
.../Universal/Pei/PlatformPei/PlatformPei.inf | 82 ++
5 files changed, 633 insertions(+)
create mode 100644 Platform/RiscV/SiFive/U500Pkg/Universal/Pei/PlatformPei/Fv.c
create mode 100644
Platform/RiscV/SiFive/U500Pkg/Universal/Pei/PlatformPei/MemDetect.c
create mode 100644
Platform/RiscV/SiFive/U500Pkg/Universal/Pei/PlatformPei/Platform.c
create mode 100644
Platform/RiscV/SiFive/U500Pkg/Universal/Pei/PlatformPei/Platform.h
create mode 100644
Platform/RiscV/SiFive/U500Pkg/Universal/Pei/PlatformPei/PlatformPei.inf
diff --git a/Platform/RiscV/SiFive/U500Pkg/Universal/Pei/PlatformPei/Fv.c
b/Platform/RiscV/SiFive/U500Pkg/Universal/Pei/PlatformPei/Fv.c
new file mode 100644
index 000..04ac7ac
--- /dev/null
+++ b/Platform/RiscV/SiFive/U500Pkg/Universal/Pei/PlatformPei/Fv.c
@@ -0,0 +1,55 @@
+/** @file
+ Build FV related hobs for platform.
+
+ Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights
reserved.
+ Copyright (c) 2006 - 2013, Intel Corporation. All rights reserved.
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD
License
+ which accompanies this distribution. The full text of the license may be
found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include "PiPei.h"
+#include "Platform.h"
+#include
+#include
+#include
+#include
+
+/**
+ Publish PEI & DXE (Decompressed) Memory based FVs to let PEI
+ and DXE know about them.
+
+ @retval EFI_SUCCESS Platform PEI FVs were initialized successfully.
+
+**/
+EFI_STATUS
+PeiFvInitialization (
+ VOID
+ )
+{
+ DEBUG ((EFI_D_INFO, "Platform PEI Firmware Volume Initialization\n"));
+ //
+ // Let DXE know about the DXE FV
+ //
+ BuildFvHob (PcdGet32 (PcdRiscVDxeFvBase), PcdGet32 (PcdRiscVDxeFvSize));
+ DEBUG ((EFI_D_INFO, "Platform builds DXE FV at %x, size %x.\n", PcdGet32
(PcdRiscVDxeFvBase), PcdGet32 (PcdRiscVDxeFvSize)));
+
+ //
+ // Let PEI know about the DXE FV so it can find the DXE Core
+ //
+ PeiServicesInstallFvInfoPpi (
+NULL,
+(VOID *)(UINTN) PcdGet32 (PcdRiscVDxeFvBase),
+PcdGet32 (PcdRiscVDxeFvSize),
+NULL,
+NULL
+);
+
+ return EFI_SUCCESS;
+}
diff --git
a/Platform/RiscV/SiFive/U500Pkg/Universal/Pei/PlatformPei/MemDetect.c
b/Platform/RiscV/SiFive/U500Pkg/Universal/Pei/PlatformPei/MemDetect.c
new file mode 100644
index 000..3c047f1
--- /dev/null
+++ b/Platform/RiscV/SiFive/U500Pkg/Universal/Pei/PlatformPei/MemDetect.c
@@ -0,0 +1,80 @@
+/**@file
+ Memory Detection for Virtual Machines.
+
+ Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights
reserved.
+ Copyright (c) 2006 - 2014, Intel Corporation. All rights reserved.
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD
License
+ which accompanies this distribution. The full text of the license may be
found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+Module Name:
+
+ MemDetect.c
+
+**/
+
+//
+// The package level header files this module uses
+//
+#include
+
+//
+// The Library classes this module consumes
+//
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "Platform.h"
+
+
+/**
+ Publish PEI core memory
+
+ @return EFI_SUCCESS The PEIM initialized successfully.
+
+**/
+EFI_STATUS
+PublishPeiMemory (
+ VOID
+ )
+{
+ EFI_STATUS Status;
+ EFI_PHYSICAL_ADDRESSMemoryBase;
+ UINT64 MemorySize;
+
+ MemoryBase = 0x8000UL + 0x100UL;
+ MemorySize = 0x4000UL - 0x100UL; //1GB - 16MB
+
+ DEBUG((EFI_D_INFO, "%a: MemoryBase:0x%x MemorySize:%d\n", __FUNCTION__,
MemoryBase, MemorySize));
+
+ //
+ // Publish this memory to the PEI Core
+ //
+ Status = PublishSystemMemory(MemoryBase, MemorySize);
+ ASSERT_EFI_ERROR (Status);
+
+ return Status;
+}
+
+/**
+ Publish system RAM and reserve memory regions
+
+**/
+VOID
+InitializeRamRegions (
+ VOID
+ )
+{
+ AddMemoryRangeHob(0x8100UL, 0x8100UL + 0x3F00UL);
+
+}
diff --git a/Platform/RiscV/SiFive/U500Pkg/Universal/Pei/PlatformPei/Platform.c
[edk2-devel] [PATCH 13/15] [platforms/devel-riscv]: U500Pkg/TimerDxe: Platform Timer DXE driver
Timer DXE driver for U500 platform based U500 platform implementation specifc
timer registers.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Gilbert Chen
---
.../SiFive/U500Pkg/Universal/Dxe/TimerDxe/Timer.c | 317 +
.../SiFive/U500Pkg/Universal/Dxe/TimerDxe/Timer.h | 179
.../U500Pkg/Universal/Dxe/TimerDxe/Timer.uni | Bin 0 -> 1678 bytes
.../U500Pkg/Universal/Dxe/TimerDxe/TimerDxe.inf| 54
.../U500Pkg/Universal/Dxe/TimerDxe/TimerExtra.uni | Bin 0 -> 1374 bytes
5 files changed, 550 insertions(+)
create mode 100644 Platform/RiscV/SiFive/U500Pkg/Universal/Dxe/TimerDxe/Timer.c
create mode 100644 Platform/RiscV/SiFive/U500Pkg/Universal/Dxe/TimerDxe/Timer.h
create mode 100644
Platform/RiscV/SiFive/U500Pkg/Universal/Dxe/TimerDxe/Timer.uni
create mode 100644
Platform/RiscV/SiFive/U500Pkg/Universal/Dxe/TimerDxe/TimerDxe.inf
create mode 100644
Platform/RiscV/SiFive/U500Pkg/Universal/Dxe/TimerDxe/TimerExtra.uni
diff --git a/Platform/RiscV/SiFive/U500Pkg/Universal/Dxe/TimerDxe/Timer.c
b/Platform/RiscV/SiFive/U500Pkg/Universal/Dxe/TimerDxe/Timer.c
new file mode 100644
index 000..8f8eeb6
--- /dev/null
+++ b/Platform/RiscV/SiFive/U500Pkg/Universal/Dxe/TimerDxe/Timer.c
@@ -0,0 +1,317 @@
+/** @file
+ RISC-V Timer Architectural Protocol for U500 platform.
+
+ Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights
reserved.
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD
License
+ which accompanies this distribution. The full text of the license may be
found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+**/
+
+#include "Timer.h"
+#include
+#include
+#include
+#include
+#include
+
+#define CLINT_REG_MTIME 0x0200BFF8
+#define CLINT_REG_MTIMECMP0 0x02004000
+#define CLINT_REG_MTIMECMP1 0x02004008
+#define CLINT_REG_MTIMECMP2 0x02004010
+#define CLINT_REG_MTIMECMP3 0x02004018
+#define CLINT_REG_MTIMECMP4 0x02004020
+
+static volatile void * const p_mtime = (void *)CLINT_REG_MTIME;
+#define MTIME (*p_mtime)
+#define MTIMECMP(i)(p_mtimecmp[i])
+
+//
+// The handle onto which the Timer Architectural Protocol will be installed
+//
+EFI_HANDLEmTimerHandle = NULL;
+
+//
+// The Timer Architectural Protocol that this driver produces
+//
+EFI_TIMER_ARCH_PROTOCOL mTimer = {
+ TimerDriverRegisterHandler,
+ TimerDriverSetTimerPeriod,
+ TimerDriverGetTimerPeriod,
+ TimerDriverGenerateSoftInterrupt
+};
+
+//
+// Pointer to the CPU Architectural Protocol instance
+//
+EFI_CPU_ARCH_PROTOCOL *mCpu;
+
+//
+// The notification function to call on every timer interrupt.
+// A bug in the compiler prevents us from initializing this here.
+//
+EFI_TIMER_NOTIFY mTimerNotifyFunction;
+
+//
+// The current period of the timer interrupt
+//
+volatile UINT64 mTimerPeriod = 0;
+
+
+/**
+ 8254 Timer #0 Interrupt Handler.
+
+ @param InterruptTypeThe type of interrupt that occured
+ @param SystemContextA pointer to the system context when the interrupt
occured
+**/
+
+VOID
+EFIAPI
+TimerInterruptHandler (
+ IN EFI_EXCEPTION_TYPE InterruptType,
+ IN EFI_SYSTEM_CONTEXT SystemContext
+ )
+{
+ EFI_TPL OriginalTPL;
+ UINT64 RiscvTimer;
+
+ csr_clear(CSR_SIE, MIP_STIP); // enable timer int
+ OriginalTPL = gBS->RaiseTPL (TPL_HIGH_LEVEL);
+ if (mTimerPeriod == 0) {
+gBS->RestoreTPL (OriginalTPL);
+mCpu->DisableInterrupt(mCpu);
+return;
+ }
+ if (mTimerNotifyFunction != NULL) {
+mTimerNotifyFunction (mTimerPeriod);
+ }
+ gBS->RestoreTPL (OriginalTPL);
+
+
+ RiscvTimer = readq_relaxed(p_mtime);
+ sbi_set_timer(RiscvTimer += mTimerPeriod);
+ csr_set(CSR_SIE, MIP_STIP); // enable timer int
+
+}
+
+/**
+
+ This function registers the handler NotifyFunction so it is called every time
+ the timer interrupt fires. It also passes the amount of time since the last
+ handler call to the NotifyFunction. If NotifyFunction is NULL, then the
+ handler is unregistered. If the handler is registered, then EFI_SUCCESS is
+ returned. If the CPU does not support registering a timer interrupt handler,
+ then EFI_UNSUPPORTED is returned. If an attempt is made to register a
handler
+ when a handler is already registered, then EFI_ALREADY_STARTED is returned.
+ If an attempt is made to unregister a handler when a handler is not
registered,
+ then EFI_INVALID_PARAMETER is returned. If an error occurs attempting to
+ register the NotifyFunction with the timer interrupt, then EFI_DEVICE_ERROR
+ is returned.
+
+ @param This The EFI_TIMER_ARCH_PROTOCOL instance.
+ @param NotifyFunction The function to call when a timer interrupt fires.
This
+ function executes at TPL_HIGH_LEVEL. The
[edk2-devel] [PATCH 03/15] [platforms/devel-riscv]: platforms/RiscV: Initial version of RISC-V platform package
Initial version of RISC-V platform package which provides the common libraries,
drivers, PCD and etc. for RISC-V platform development.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Gilbert Chen
---
Platform/RiscV/Readme.md | 88 +++
Platform/RiscV/RiscVPlatformPkg.dec | 75 ++
Platform/RiscV/RiscVPlatformPkg.uni | Bin 0 -> 1754 bytes
Platform/RiscV/RiscVPlatformPkgExtra.uni | Bin 0 -> 1392 bytes
4 files changed, 163 insertions(+)
create mode 100644 Platform/RiscV/Readme.md
create mode 100644 Platform/RiscV/RiscVPlatformPkg.dec
create mode 100644 Platform/RiscV/RiscVPlatformPkg.uni
create mode 100644 Platform/RiscV/RiscVPlatformPkgExtra.uni
diff --git a/Platform/RiscV/Readme.md b/Platform/RiscV/Readme.md
new file mode 100644
index 000..dd817eb
--- /dev/null
+++ b/Platform/RiscV/Readme.md
@@ -0,0 +1,88 @@
+# Introduction
+
+## EDK2 RISC-V Platform Package
+RISC-V platform package provides the generic and common modules for RISC-V
platforms. RISC-V platform package could include RiscPlatformPkg.dec to use the
common drivers, libraries, definitions, PCDs and etc. for the platform
development.
+
+## EDK2 RISC-V Platforms
+RISC-V platform is created and maintained by RISC-V platform vendors. The
directory of RISC-V platform should be created under Platform/RiscV. Vendor
should create the folder under Platform/RiscV and name it using vendor name,
under the vendor folder is the platform folder named by platform model name,
code name or etc. (e.g. Platform/RiscV/SiFive/U500Pkg)
+
+## Build EDK2 RISC-V Platforms
+RISC-V platform package should provide EDK2 metafiles under RISC-V platform
package folder (Platform/RiscV/{Vendor}/{Platform}). Build RISC-V platform
package against edk2 and follow the build guidence mentioned in Readme.md under
below link.
+https://github.com/tianocore/edk2-platforms
+
+### Download the sources ###
+```
+git clone https://github.com/tianocore/edk2-staging.git
+# Checkout RISC-V branch
+git clone https://github.com/tianocore/edk2-platforms.git
+# Checkout devel-riscv branch
+git clone https://github.com/tianocore/edk2-non-osi.git
+```
+
+### Requirements
+Build EDK2 RISC-V platform requires GCC RISC-V toolchain. Refer to
https://github.com/riscv/riscv-gnu-toolchain for the details.
+
+### EDK2 project
+Currently, the EDK2 RISC-V platform can only build with edk2 project in
**edk2-staging/RISC-V** branch. The build architecture whcih is supported and
verified so far is "RISCV64". The verified RISC-V toolchain is GCC 7.1.1,
toolchain tag is "GCC711RISCV" declared in tools_def.txt
+
+### Linux Build Instructions
+You can build the RISC-V platform using below script,
+`build -a RISCV64 -p Platform/{Vendor}/{Platform}/{Platform}.dsc -t
GCC711RISCV`
+
+Or modify target.txt to set up your build parameters.
+
+## RISC-V Platform PCD settings
+### EDK2 Firmware Volume Settings
+EDK2 Firmware volume related PCDs which declared in platform FDF file.
+
+| **PCD name** |**Usage**|
+||--|
+|PcdRiscVSecFvBase| The base address of SEC Firmware Volume|
+|PcdRiscVSecFvSize| The size of SEC Firmware Volume|
+|PcdRiscVPeiFvBase| The base address of SEC Firmware Volume|
+|PcdRiscVPeiFvSize| The size of SEC Firmware Volume|
+|PcdRiscVDxeFvBase| The base address of SEC Firmware Volume|
+|PcdRiscVDxeFvSize| The size of SEC Firmware Volume|
+
+### EDK2 EFI Variable Region Settings
+The PCD settings regard to EFI Variable
+
+| **PCD name** |**Usage**|
+||--|
+|PcdVariableFdBaseAddress| The EFI variable firmware device base address|
+|PcdVariableFdSize| The EFI variable firmware device size|
+|PcdVariableFdBlockSize| The block size of EFI variable firmware device|
+|PcdPlatformFlashNvStorageVariableBase| EFI variable base address within
firmware device|
+|PcdPlatformFlashNvStorageFtwWorkingBase| The base address of EFI variable
fault tolerance worksapce (FTW) within firmware device|
+|PcdPlatformFlashNvStorageFtwSpareBase| The base address of EFI variable spare
FTW within firmware device|
+
+### RISC-V Physical Memory Protection (PMP) Region Settings
+Below PCDs could be set in platform FDF file.
+
+| **PCD name** |**Usage**|
+||--|
+|PcdFwStartAddress| The starting address of firmware region to protected by
PMP|
+|PcdFwEndAddress| The ending address of firmware region to protected by PMP|
+
+### RISC-V Processor HART Settings
+
+| **PCD name** |**Usage**|
+||--|
+|PcdHartCount| Number of RISC-V HARTs, the value is processor-implementation
specific|
+|PcdBootHartId| The ID of RISC-V HART to execute main fimrware code and boot
system to OS|
+
+### RISC-V OpenSBI Settings
+
+| **PCD name** |**Usage**|
+||--|
+|PcdScratchRamBase| The base address of OpenSBI scratch buffer for all RISC-V
HARTs|
+|PcdScratchRamSize| The total size of OpenSBI scratch buffer for
